From mboxrd@z Thu Jan 1 00:00:00 1970 From: ville.syrjala@linux.intel.com Subject: [PATCH 0/2] drm/i915: VLV clock gating fixes Date: Tue, 21 May 2013 18:01:48 +0300 Message-ID: <1369148510-22461-1-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id E22FFE6121 for ; Tue, 21 May 2013 08:01:59 -0700 (PDT) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org I spotted a few invalid register accesses in valleyview_init_clock_gating() while trawling through the clock gating code. This series tries to fix them. Compile tested only.