From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH] drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence Date: Thu, 11 Jul 2013 17:11:41 +0300 Message-ID: <1373551901.12949.14.camel@intelbox> References: <1370432073-27634-30-git-send-email-daniel.vetter@ffwll.ch> <1370506973-11989-1-git-send-email-daniel.vetter@ffwll.ch> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1826808402==" Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 9C268E650B for ; Thu, 11 Jul 2013 07:12:06 -0700 (PDT) In-Reply-To: <1370506973-11989-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Jani Nikula , Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org --===============1826808402== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-Sk9kwOlgx/UT85Ucgp+Y" --=-Sk9kwOlgx/UT85Ucgp+Y Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 2013-06-06 at 10:22 +0200, Daniel Vetter wrote: > No need to call the ->pre_pll_enable hook twice if we don't enable the > dpll too early. This should make Jani a bit less grumpy. >=20 > v2: Rebase on top of the newly-colored BUG_ONs. >=20 > Cc: Jani Nikula > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/i915/intel_display.c | 45 +++++++++++++++---------------= ------ > 1 file changed, 18 insertions(+), 27 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 5e43b9a..6e4d666 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1268,32 +1268,38 @@ static void assert_pch_ports_disabled(struct drm_= i915_private *dev_priv, > assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); > } > =20 > -static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe = pipe) > +static void vlv_enable_pll(struct intel_crtc *crtc) > { > - int reg; > - u32 val; > + struct drm_device *dev =3D crtc->base.dev; > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + int reg =3D DPLL(crtc->pipe); > + u32 dpll =3D crtc->config.dpll_hw_state.dpll; > =20 > - assert_pipe_disabled(dev_priv, pipe); > + assert_pipe_disabled(dev_priv, crtc->pipe); > =20 > /* No really, not for ILK+ */ > BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); > =20 > /* PLL is protected by panel, make sure we can write it */ > if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) > - assert_panel_unlocked(dev_priv, pipe); > + assert_panel_unlocked(dev_priv, crtc->pipe); > + > + I915_WRITE(reg, dpll); > + POSTING_READ(reg); > + udelay(150); > + > + if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) =3D=3D DPLL_LOCK_VLV), 1= )) > + DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); > =20 > - reg =3D DPLL(pipe); > - val =3D I915_READ(reg); > - val |=3D DPLL_VCO_ENABLE; > =20 > /* We do this three times for luck */ > - I915_WRITE(reg, val); > + I915_WRITE(reg, dpll); > POSTING_READ(reg); > udelay(150); /* wait for warmup */ > - I915_WRITE(reg, val); > + I915_WRITE(reg, dpll); > POSTING_READ(reg); > udelay(150); /* wait for warmup */ > - I915_WRITE(reg, val); > + I915_WRITE(reg, dpll); > POSTING_READ(reg); > udelay(150); /* wait for warmup */ > } > @@ -3561,7 +3567,7 @@ static void valleyview_crtc_enable(struct drm_crtc = *crtc) > if (encoder->pre_pll_enable) > encoder->pre_pll_enable(encoder); > =20 > - vlv_enable_pll(dev_priv, pipe); > + vlv_enable_pll(intel_crtc); > =20 > for_each_encoder_on_crtc(dev, crtc, encoder) > if (encoder->pre_enable) > @@ -4315,7 +4321,6 @@ static void vlv_update_pll(struct intel_crtc *crtc) > { > struct drm_device *dev =3D crtc->base.dev; > struct drm_i915_private *dev_priv =3D dev->dev_private; > - struct intel_encoder *encoder; > int pipe =3D crtc->pipe; > u32 dpll, mdiv; > u32 bestn, bestm1, bestm2, bestp1, bestp2; > @@ -4403,10 +4408,6 @@ static void vlv_update_pll(struct intel_crtc *crtc= ) > =20 > vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000); > =20 > - for_each_encoder_on_crtc(dev, &crtc->base, encoder) > - if (encoder->pre_pll_enable) > - encoder->pre_pll_enable(encoder); > - > /* Enable DPIO clock input */ > dpll =3D DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | > DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; > @@ -4416,20 +4417,10 @@ static void vlv_update_pll(struct intel_crtc *crt= c) > dpll |=3D DPLL_VCO_ENABLE; > crtc->config.dpll_hw_state.dpll =3D dpll; > =20 > - I915_WRITE(DPLL(pipe), dpll); > - POSTING_READ(DPLL(pipe)); > - udelay(150); > - > - if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) =3D=3D DPLL_LOCK_= VLV), 1)) > - DRM_ERROR("DPLL %d failed to lock\n", pipe); > - > dpll_md =3D (crtc->config.pixel_multiplier - 1) > << DPLL_MD_UDI_MULTIPLIER_SHIFT; > crtc->config.dpll_hw_state.dpll_md =3D dpll_md; > =20 > - I915_WRITE(DPLL_MD(pipe), dpll_md); > - POSTING_READ(DPLL_MD(pipe)); This piece was not added to vlv_enable_pll. Other than this patches 29-31 look ok, so on those: Reviewed-by: Imre Deak --=-Sk9kwOlgx/UT85Ucgp+Y Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQEcBAABAgAGBQJR3r0dAAoJEORIIAnNuWDF08MIAOoqhHiB0ZiGn//aq0RMlI27 tUd9mV9X1N5TSJwKBQliELFV2ELiA5vK4BOpAZi+oywOt+iLyZ29NwEcKqXifsqC TNZ0TjzmI9bioU3scdLPgzUbROrte3c9uqrm3EvXdR2G/GX1+uXzWZAHbCzJf4a6 j8fdnqamPo7oWO6fKDiiUb0+qTSKUodT6McJFWGU0sjsJg+9CfiG/QC3RH5SPE6P Ho3OGYXBtj7gd9q2bpuJg+Qc0jhR0qNsiczBUE0G/SrvlVxO+Xy71diwpoMrwnDB zJcQbWDdmzWvp6KzAqGlpr/VbPY2PLm5flSvkSr0Gl7pIUVn92H5PaTlBB0in9U= =MzEc -----END PGP SIGNATURE----- --=-Sk9kwOlgx/UT85Ucgp+Y-- --===============1826808402== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1826808402==--