From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 06/15] drm/i915: use INTEL_IRQ_REG_INIT on VLV too Date: Tue, 23 Jul 2013 19:33:46 -0300 Message-ID: <1374618835-28120-7-git-send-email-przanoni@gmail.com> References: <1374618835-28120-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-yh0-f50.google.com (mail-yh0-f50.google.com [209.85.213.50]) by gabe.freedesktop.org (Postfix) with ESMTP id 51C22E6792 for ; Tue, 23 Jul 2013 15:34:58 -0700 (PDT) Received: by mail-yh0-f50.google.com with SMTP id a41so767682yho.23 for ; Tue, 23 Jul 2013 15:34:57 -0700 (PDT) In-Reply-To: <1374618835-28120-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni This is a case where the code written doesn't match INTEL_IRQ_REG_INIT perfectly. Call it after clearing PIPESTAT so we make sure that it is cleared while the interrupts are disabled. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_irq.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index e416848..37420b5 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2236,12 +2236,9 @@ static int valleyview_irq_postinstall(struct drm_device *dev) I915_WRITE(PORT_HOTPLUG_EN, 0); POSTING_READ(PORT_HOTPLUG_EN); - I915_WRITE(VLV_IMR, dev_priv->irq_mask); - I915_WRITE(VLV_IER, enable_mask); - I915_WRITE(VLV_IIR, 0xffffffff); I915_WRITE(PIPESTAT(0), 0xffff); I915_WRITE(PIPESTAT(1), 0xffff); - POSTING_READ(VLV_IER); + INTEL_IRQ_REG_INIT(VLV_I, true, enable_mask, dev_priv->irq_mask); /* Interrupt setup is already guaranteed to be single-threaded, this is * just to make the assert_spin_locked check happy. */ -- 1.8.1.2