From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: [PATCH] assembler: error for the wrong syntax of SEND instruction on GEN6+ Date: Wed, 14 Aug 2013 14:21:16 -0700 Message-ID: <1376515276-25541-1-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id E1199E5FFE for ; Wed, 14 Aug 2013 14:22:01 -0700 (PDT) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org From: "Xiang, Haihao" predicate SEND execsize dst sendleadreg payload directsrcoperand instoptions predicate SEND execsize dst sendleadreg payload imm32reg instoptions predicate SEND execsize dst sendleadreg payload sndopr imm32reg instoptions predicate SEND execsize dst sendleadreg payload exp directsrcoperand instoptions The above four syntaxes are only used on legacy platforms which support implied move from payload to dst. Signed-off-by: Xiang, Haihao Signed-off-by: Ben Widawsky --- Somehow this ended up in our internal IGT. Anyone have an issue with me pushing it to igt proper? --- assembler/gram.y | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/assembler/gram.y b/assembler/gram.y index e58c1fe..8795797 100644 --- a/assembler/gram.y +++ b/assembler/gram.y @@ -1215,6 +1215,9 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget } | predicate sendop execsize dst sendleadreg payload directsrcoperand instoptions { + if (IS_GENp(6)) + error(&@2, "the syntax of send instruction\n"); + memset(&$$, 0, sizeof($$)); set_instruction_opcode(&$$, $2); GEN(&$$)->header.destreg__conditionalmod = $5.nr; /* msg reg index */ @@ -1233,6 +1236,9 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget } | predicate sendop execsize dst sendleadreg payload imm32reg instoptions { + if (IS_GENp(6)) + error(&@2, "the syntax of send instruction\n"); + if ($7.reg.type != BRW_REGISTER_TYPE_UD && $7.reg.type != BRW_REGISTER_TYPE_D && $7.reg.type != BRW_REGISTER_TYPE_V) { @@ -1336,6 +1342,9 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget } | predicate sendop execsize dst sendleadreg payload sndopr imm32reg instoptions { + if (IS_GENp(6)) + error(&@2, "the syntax of send instruction\n"); + if ($8.reg.type != BRW_REGISTER_TYPE_UD && $8.reg.type != BRW_REGISTER_TYPE_D && $8.reg.type != BRW_REGISTER_TYPE_V) { @@ -1355,15 +1364,16 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget if (set_instruction_src1(&$$, &$8, &@8) != 0) YYERROR; - if (IS_GENp(8)) { - gen8_set_eot(GEN8(&$$), !!($7 & EX_DESC_EOT_MASK)); - } else if (IS_GENx(5)) { + if (IS_GENx(5)) { GEN(&$$)->bits2.send_gen5.sfid = ($7 & EX_DESC_SFID_MASK); GEN(&$$)->bits3.generic_gen5.end_of_thread = !!($7 & EX_DESC_EOT_MASK); } } | predicate sendop execsize dst sendleadreg payload exp directsrcoperand instoptions { + if (IS_GENp(6)) + error(&@2, "the syntax of send instruction\n"); + memset(&$$, 0, sizeof($$)); set_instruction_opcode(&$$, $2); GEN(&$$)->header.destreg__conditionalmod = $5.nr; /* msg reg index */ -- 1.8.3.4