Re: [PATCH 4/8] drm/i915: Fix HSW parity test

Ville Syrjälä
2013-09-13T08:17:42Z

On Thu, Sep 12, 2013 at 10:28:30PM -0700, Ben Widawsky wrote:
> Haswell changed the log registers to be WO, so we can no longer read
> them to determine the programming (which sucks, see later note). For
> now, simply use the cached value, and hope HW doesn't screw us over.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57441
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_sysfs.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index d572435..43c2e81 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -133,6 +133,19 @@ i915_l3_read(struct file *filp, struct kobject *kobj,
> if (ret)
> return ret;
>
> + if (IS_HASWELL(drm_dev)) {
> + int last = min_t(int, GEN7_L3LOG_SIZE, count + offset);
> + if ((!dev_priv->l3_parity.remap_info))
^^

Also could just flip the if vs. else branches around to avoid the '!'.

> + memset(buf + offset, 0, last - offset);
> + else
> + memcpy(buf + offset,
> + dev_priv->l3_parity.remap_info + (offset/4),
> + last - offset);
> +
> + i = last;

And it looks like this didn't get updated after we bikesh(r)edded the
register read part. It should just be:

if (...)
memset(buf, 0, count);
else
memcpy(buf, dev_priv->l3_parity.remap_info + (offset/4), count);

> + goto out;
> + }
> +
> misccpctl = I915_READ(GEN7_MISCCPCTL);
> I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
>
> @@ -141,6 +154,7 @@ i915_l3_read(struct file *filp, struct kobject *kobj,

> I915_WRITE(GEN7_MISCCPCTL, misccpctl);
>
> +out:
> mutex_unlock(&drm_dev->struct_mutex);
>
> return i;
> --
> 1.8.4
>
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--
Ville Syrjälä
Intel OTC