From: Ben Widawsky <benjamin.widawsky@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: bryan.j.bell@intel.com,
Ben Widawsky <benjamin.widawsky@intel.com>,
Ben Widawsky <ben@bwidawsk.net>,
vishnu.venkatesh@intel.com
Subject: [PATCH 8/8] drm/i915: Do remaps for all contexts
Date: Thu, 12 Sep 2013 22:28:34 -0700 [thread overview]
Message-ID: <1379050122-12774-9-git-send-email-benjamin.widawsky@intel.com> (raw)
In-Reply-To: <1379050122-12774-1-git-send-email-benjamin.widawsky@intel.com>
On both Ivybridge and Haswell, row remapping information is saved and
restored with context. This means, we never actually properly supported
the l3 remapping because our sysfs interface is asynchronous (and not
tied to any context), and the known faulty HW would be reused by the
next context to run.
Not that due to the asynchronous nature of the sysfs entry, there is no
point modifying the registers for the existing context. Instead we set a
flag for all contexts to load the correct remapping information on the
next run. Interested clients can use debugfs to determine whether or not
the row has been remapped.
One could propose at this point that we just do the remapping in the
kernel. I guess since we have to maintain the sysfs interface anyway,
I'm not sure how useful it is, and I do like keeping the policy in
userspace; (it wasn't my original decision to make the
interface the way it is, so I'm not attached).
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_debugfs.c | 8 +++++++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem_context.c | 17 +++++++++++++--
drivers/gpu/drm/i915/i915_sysfs.c | 38 +++++++++++----------------------
4 files changed, 36 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ada0950..80bed69 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -145,6 +145,13 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
seq_printf(m, " (%s)", obj->ring->name);
}
+static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
+{
+ seq_putc(m, ctx->is_initialized ? 'I' : 'i');
+ seq_putc(m, ctx->remap_slice ? 'R' : 'r');
+ seq_putc(m, ' ');
+}
+
static int i915_gem_object_list_info(struct seq_file *m, void *data)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -1463,6 +1470,7 @@ static int i915_context_status(struct seq_file *m, void *unused)
list_for_each_entry(ctx, &dev_priv->context_list, link) {
seq_puts(m, "HW context ");
+ describe_ctx(m, ctx);
for_each_ring(ring, dev_priv, i)
if (ring->default_context == ctx)
seq_printf(m, "(default context %s) ", ring->name);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 68f992b..6ba78cd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -602,6 +602,7 @@ struct i915_hw_context {
struct kref ref;
int id;
bool is_initialized;
+ uint8_t remap_slice;
struct drm_i915_file_private *file_priv;
struct intel_ring_buffer *ring;
struct drm_i915_gem_object *obj;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 2bbdce8..72b7202 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -140,7 +140,7 @@ create_hw_context(struct drm_device *dev,
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct i915_hw_context *ctx;
- int ret;
+ int ret, i;
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
if (ctx == NULL)
@@ -181,6 +181,8 @@ create_hw_context(struct drm_device *dev,
ctx->file_priv = file_priv;
ctx->id = ret;
+ for (i = 0; i < NUM_L3_SLICES(dev); i++)
+ ctx->remap_slice |= 1 << 1;
return ctx;
@@ -396,7 +398,7 @@ static int do_switch(struct i915_hw_context *to)
struct intel_ring_buffer *ring = to->ring;
struct i915_hw_context *from = ring->last_context;
u32 hw_flags = 0;
- int ret;
+ int ret, i;
BUG_ON(from != NULL && from->obj != NULL && from->obj->pin_count == 0);
@@ -432,6 +434,17 @@ static int do_switch(struct i915_hw_context *to)
return ret;
}
+ for (i = 0; i < MAX_L3_SLICES; i++) {
+ if (!(to->remap_slice & (1<<i)))
+ continue;
+
+ ret = i915_gem_l3_remap(ring, i);
+ if (!ret) {
+ to->remap_slice &= ~(1<<i);
+ }
+ /* If it failed, try again next round */
+ }
+
/* The backing object for the context is done after switching to the
* *next* context. Therefore we cannot retire the previous context until
* the next context has already started running. In fact, the below code
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 65a7274..f0d7e1c 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -118,9 +118,8 @@ i915_l3_read(struct file *filp, struct kobject *kobj,
struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
struct drm_device *drm_dev = dminor->dev;
struct drm_i915_private *dev_priv = drm_dev->dev_private;
- uint32_t misccpctl;
int slice = (int)(uintptr_t)attr->private;
- int i, ret;
+ int ret;
count = round_down(count, 4);
@@ -134,31 +133,16 @@ i915_l3_read(struct file *filp, struct kobject *kobj,
if (ret)
return ret;
- if (IS_HASWELL(drm_dev)) {
- int last = min_t(int, GEN7_L3LOG_SIZE, count + offset);
- if ((!dev_priv->l3_parity.remap_info[slice]))
- memset(buf + offset, 0, last - offset);
- else
- memcpy(buf + offset,
- dev_priv->l3_parity.remap_info[slice] + (offset/4),
- last - offset);
-
- i = last;
- goto out;
- }
-
- misccpctl = I915_READ(GEN7_MISCCPCTL);
- I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
-
- for (i = 0; i < count; i += 4)
- *((uint32_t *)(&buf[i])) = I915_READ(GEN7_L3LOG_BASE + offset + i);
-
- I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+ if ((!dev_priv->l3_parity.remap_info[slice]))
+ memset(buf + offset, 0, count);
+ else
+ memcpy(buf + offset,
+ dev_priv->l3_parity.remap_info[slice] + (offset/4),
+ count);
-out:
mutex_unlock(&drm_dev->struct_mutex);
- return i;
+ return count;
}
static ssize_t
@@ -170,6 +154,7 @@ i915_l3_write(struct file *filp, struct kobject *kobj,
struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
struct drm_device *drm_dev = dminor->dev;
struct drm_i915_private *dev_priv = drm_dev->dev_private;
+ struct i915_hw_context *ctx;
u32 *temp = NULL; /* Just here to make handling failures easy */
int slice = (int)(uintptr_t)attr->private;
int ret;
@@ -206,8 +191,9 @@ i915_l3_write(struct file *filp, struct kobject *kobj,
memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count);
- if (i915_gem_l3_remap(&dev_priv->ring[RCS], slice))
- count = 0;
+ /* NB: We defer the remapping until we switch to the context */
+ list_for_each_entry(ctx, &dev_priv->context_list, link)
+ ctx->remap_slice |= (1<<slice);
mutex_unlock(&drm_dev->struct_mutex);
--
1.8.4
next prev parent reply other threads:[~2013-09-13 5:29 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-13 5:28 [PATCH 0/8] DPF (GPU l3 parity detection) improvements Ben Widawsky
2013-09-13 5:28 ` [PATCH 1/8] drm/i915: Remove extra "ring" Ben Widawsky
2013-09-13 5:28 ` [PATCH 2/8] drm/i915: Round l3 parity reads down Ben Widawsky
2013-09-13 5:28 ` [PATCH 3/8] drm/i915: Fix l3 parity user buffer offset Ben Widawsky
2013-09-13 12:56 ` Daniel Vetter
2013-09-13 5:28 ` [PATCH 4/8] drm/i915: Fix HSW parity test Ben Widawsky
2013-09-13 8:17 ` Ville Syrjälä
2013-09-13 5:28 ` [PATCH 5/8] drm/i915: Add second slice l3 remapping Ben Widawsky
2013-09-13 9:38 ` Ville Syrjälä
2013-09-17 18:45 ` Ben Widawsky
2013-09-17 18:51 ` Bell, Bryan J
2013-09-17 19:02 ` Ville Syrjälä
2013-09-17 19:08 ` Bell, Bryan J
2013-09-13 5:28 ` [PATCH 6/8] drm/i915: Make l3 remapping use the ring Ben Widawsky
2013-09-13 16:16 ` Daniel Vetter
2013-09-13 5:28 ` [PATCH 7/8] drm/i915: Keep a list of all contexts Ben Widawsky
2013-09-13 5:28 ` Ben Widawsky [this message]
2013-09-13 9:17 ` [PATCH 8/8] drm/i915: Do remaps for " Ville Syrjälä
2013-09-13 9:20 ` Ville Syrjälä
2013-09-17 20:42 ` Ben Widawsky
2013-09-13 5:28 ` [PATCH 09/16] intel_l3_parity: Fix indentation Ben Widawsky
2013-09-13 5:28 ` [PATCH 10/16] intel_l3_parity: Assert all GEN7+ support Ben Widawsky
2013-09-16 18:18 ` Bell, Bryan J
2013-09-17 23:52 ` Ben Widawsky
2013-09-17 23:59 ` Ben Widawsky
2013-09-13 5:28 ` [PATCH 11/16] intel_l3_parity: Use getopt for the l3 parity tool Ben Widawsky
2013-09-13 5:28 ` [PATCH 12/16] intel_l3_parity: Hardware info argument Ben Widawsky
2013-09-13 5:28 ` [PATCH 13/16] intel_l3_parity: slice support Ben Widawsky
2013-09-13 5:28 ` [PATCH 14/16] intel_l3_parity: Actually support multiple slices Ben Widawsky
2013-09-13 5:28 ` [PATCH 15/16] intel_l3_parity: Support error injection Ben Widawsky
2013-09-13 9:12 ` Daniel Vetter
2013-09-13 15:54 ` Ben Widawsky
2013-09-13 16:14 ` Daniel Vetter
2013-09-13 16:29 ` Ben Widawsky
2013-09-13 5:28 ` [PATCH 16/16] intel_l3_parity: Support a daemonic mode Ben Widawsky
2013-09-13 9:44 ` [PATCH 0/8] DPF (GPU l3 parity detection) improvements Ville Syrjälä
2013-09-17 0:52 ` Bell, Bryan J
2013-09-17 4:15 ` Ben Widawsky
2013-09-17 7:27 ` Daniel Vetter
2013-09-17 18:23 ` Bell, Bryan J
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