From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chon Ming Lee Subject: [PATCH 1/2] drm/i915: Send a DPIO cmnreset during driver load or system resume. Date: Fri, 13 Sep 2013 14:39:20 +0800 Message-ID: <1379054361-26440-2-git-send-email-chon.ming.lee@intel.com> References: <[PATCH] drm/i915: Enable VLV to work in BIOS-less system> <1379054361-26440-1-git-send-email-chon.ming.lee@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 8FD74E6763 for ; Thu, 12 Sep 2013 23:41:23 -0700 (PDT) In-Reply-To: <1379054361-26440-1-git-send-email-chon.ming.lee@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Without the DPIO cmnreset, the PLL fail to lock. This should have done by BIOS. v2: Move this to intel_uncore_sanitize to allow it to get call during resume path. (Daniel) Signed-off-by: Chon Ming Lee --- drivers/gpu/drm/i915/intel_uncore.c | 15 +++++++++++++++ 1 files changed, 15 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 8649f1c..b1f53f3 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -276,10 +276,25 @@ static void intel_uncore_forcewake_reset(struct drm_device *dev) void intel_uncore_sanitize(struct drm_device *dev) { + struct drm_i915_private *dev_priv = dev->dev_private; + u32 reg_val; + intel_uncore_forcewake_reset(dev); /* BIOS often leaves RC6 enabled, but disable it for hw init */ intel_disable_gt_powersave(dev); + + /* Trigger DPIO CMN RESET, require especially in BIOS less + * system + */ + if (IS_VALLEYVIEW(dev)) { + reg_val = I915_READ(DPIO_CTL); + if (!(reg_val & 0x1)) { + I915_WRITE(DPIO_CTL, 0x0); + I915_WRITE(DPIO_CTL, 0x1); + POSTING_READ(DPIO_CTL); + } + } } /* -- 1.7.7.6