[PATCH 2/2] drm/i915: Program GMBUS Frequency based on the CDCLK

[Chon Ming Lee <chon.ming.lee@intel.com>]

CDCLK is used to generate the gmbus clock.  This is normally done by
BIOS. This is only for valleyview platform.

v2: Move this to intel_i2c_reset to allow reprogram the gmbus frequency
during resume. (Daniel)

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |    8 +++++++
 drivers/gpu/drm/i915/intel_i2c.c |   43 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 51 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bcee89b..8ddf58a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -382,6 +382,8 @@
 #define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
 
 /* vlv2 north clock has */
+#define CCK_FUSE_REG				0x8
+#define  CCK_FUSE_HPLL_FREQ_MASK		0x3
 #define CCK_REG_DSI_PLL_FUSE			0x44
 #define CCK_REG_DSI_PLL_CONTROL			0x48
 #define  DSI_PLL_VCO_EN				(1 << 31)
@@ -1424,6 +1426,12 @@
 
 #define MI_ARB_VLV		(VLV_DISPLAY_BASE + 0x6504)
 
+#define CZCLK_CDCLK_FREQ_RATIO	(dev_priv->info->display_mmio_offset + 0x6508)
+#define   CDCLK_FREQ_SHIFT	4
+#define   CDCLK_FREQ_MASK	0x1f
+#define   CZCLK_FREQ_MASK	0xf
+#define GMBUS_FREQ		(dev_priv->info->display_mmio_offset + 0x6510)
+
 /*
  * Palette regs
  */
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index d1c1e0f7..a8c4165 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -58,10 +58,53 @@ to_intel_gmbus(struct i2c_adapter *i2c)
 	return container_of(i2c, struct intel_gmbus, adapter);
 }
 
+static void gmbus_set_freq(struct drm_i915_private *dev_priv)
+{
+	int cdclk_ratio[] = { 10, 15, 20, 25, 30, 0, 40, 45, 50, 0,
+			60, 0, 0, 75, 80, 0, 90, 0, 100, 0,
+			0, 0, 120, 0, 0, 0, 0, 0, 150, 0, 160 };
+	int vco_freq[] = { 800, 1600, 2000, 2400 };
+	int gmbus_freq = 0, cdclk, hpll_freq;
+	u32 reg_val;
+
+	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
+
+	/* Obtain SKU information to determine the correct CDCLK */
+	mutex_lock(&dev_priv->dpio_lock);
+	reg_val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
+	mutex_unlock(&dev_priv->dpio_lock);
+
+	hpll_freq = reg_val & CCK_FUSE_HPLL_FREQ_MASK;
+
+	/* Get the CDCLK frequency */
+	reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO);
+
+	cdclk = ((reg_val >> CDCLK_FREQ_SHIFT) & CDCLK_FREQ_MASK) - 1;
+
+	/* To enable hotplug detect, the gmbus frequency need to set as
+	 * cdclk/1.01
+	 */
+	if (cdclk_ratio[cdclk])
+		gmbus_freq = vco_freq[hpll_freq] / cdclk_ratio[cdclk] * 101 / 10;
+
+	WARN_ON(gmbus_freq == 0);
+
+	if (gmbus_freq != 0)
+		I915_WRITE(GMBUS_FREQ, gmbus_freq);
+
+}
+
 void
 intel_i2c_reset(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/* In BIOS-less system, program the correct gmbus frequency
+	 * before reading edid.
+	 */
+	if (IS_VALLEYVIEW(dev))
+		gmbus_set_freq(dev_priv);
+
 	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
 	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
 }
-- 
1.7.7.6