From: Ben Widawsky <benjamin.widawsky@intel.com>
To: Intel GFX <intel-gfx@lists.freedesktop.org>
Cc: Ben Widawsky <ben@bwidawsk.net>,
Ben Widawsky <benjamin.widawsky@intel.com>
Subject: [PATCH] [v2] drm/i915: s/HAS_L3_GPU_CACHE/HAS_L3_DPF
Date: Thu, 19 Sep 2013 10:47:31 -0700 [thread overview]
Message-ID: <1379612851-1602-1-git-send-email-benjamin.widawsky@intel.com> (raw)
In-Reply-To: <20130918075040.GC4531@intel.com>
We'd only ever used this define to denote whether or not we have the
dynamic parity feature (DPF) and never to determine whether or not L3
exists. Baytrail is a good example of where L3 exists, and not DPF.
This patch provides clarify in the code for future use cases which might
want to actually query whether or not L3 exists.
v2: Add /* DPF == dynamic parity feature */
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_drv.h | 5 +++--
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
drivers/gpu/drm/i915/i915_sysfs.c | 4 ++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++---
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 015df52..09a5c82 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1691,8 +1691,9 @@ struct drm_i915_file_private {
#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
-#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
-#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_GPU_CACHE(dev))
+/* DPF == dynamic parity feature */
+#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
+#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
#define GT_FREQUENCY_MULTIPLIER 50
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 18d07d7..7859f91 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4260,7 +4260,7 @@ int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice)
u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
int i, ret;
- if (!HAS_L3_GPU_CACHE(dev) || !remap_info)
+ if (!HAS_L3_DPF(dev) || !remap_info)
return 0;
ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1c7f6ab..cfaf434 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -960,7 +960,7 @@ static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
- if (!HAS_L3_GPU_CACHE(dev))
+ if (!HAS_L3_DPF(dev))
return;
spin_lock(&dev_priv->irq_lock);
@@ -2292,7 +2292,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
pm_irqs = gt_irqs = 0;
dev_priv->gt_irq_mask = ~0;
- if (HAS_L3_GPU_CACHE(dev)) {
+ if (HAS_L3_DPF(dev)) {
/* L3 parity interrupt is always unmasked. */
dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
gt_irqs |= GT_PARITY_ERROR(dev);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index deb8787..7b4c79c 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -97,7 +97,7 @@ static struct attribute_group rc6_attr_group = {
static int l3_access_valid(struct drm_device *dev, loff_t offset)
{
- if (!HAS_L3_GPU_CACHE(dev))
+ if (!HAS_L3_DPF(dev))
return -EPERM;
if (offset % 4 != 0)
@@ -525,7 +525,7 @@ void i915_setup_sysfs(struct drm_device *dev)
DRM_ERROR("RC6 residency sysfs setup failed\n");
}
#endif
- if (HAS_L3_GPU_CACHE(dev)) {
+ if (HAS_L3_DPF(dev)) {
ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs);
if (ret)
DRM_ERROR("l3 parity sysfs setup failed\n");
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 958b7d8..b67104a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -569,7 +569,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
if (INTEL_INFO(dev)->gen >= 6)
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
- if (HAS_L3_GPU_CACHE(dev))
+ if (HAS_L3_DPF(dev))
I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
return ret;
@@ -997,7 +997,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (ring->irq_refcount++ == 0) {
- if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
+ if (HAS_L3_DPF(dev) && ring->id == RCS)
I915_WRITE_IMR(ring,
~(ring->irq_enable_mask |
GT_PARITY_ERROR(dev)));
@@ -1019,7 +1019,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (--ring->irq_refcount == 0) {
- if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
+ if (HAS_L3_DPF(dev) && ring->id == RCS)
I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
else
I915_WRITE_IMR(ring, ~0);
--
1.8.4
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next prev parent reply other threads:[~2013-09-19 17:47 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-18 4:12 [PATCH 1/6] drm/i915: Fix HSW parity test Ben Widawsky
2013-09-18 4:12 ` [PATCH 2/6] drm/i915: Add second slice l3 remapping Ben Widawsky
2013-09-18 7:36 ` Ville Syrjälä
2013-09-18 16:22 ` Ben Widawsky
2013-09-19 18:13 ` [PATCH] [v3] " Ben Widawsky
2013-09-18 4:12 ` [PATCH 3/6] drm/i915: Make l3 remapping use the ring Ben Widawsky
2013-09-19 18:39 ` Daniel Vetter
2013-09-18 4:12 ` [PATCH 4/6] drm/i915: Keep a list of all contexts Ben Widawsky
2013-09-18 4:12 ` [PATCH 5/6] drm/i915: Do remaps for " Ben Widawsky
2013-09-18 7:48 ` Ville Syrjälä
2013-09-19 1:14 ` Ben Widawsky
2013-09-19 1:17 ` Ben Widawsky
2013-09-19 2:03 ` [PATCH] [v3] " Ben Widawsky
2013-09-18 4:12 ` [PATCH 6/6] drm/i915: s/HAS_L3_GPU_CACHE/HAS_L3_DPF Ben Widawsky
2013-09-18 7:50 ` Ville Syrjälä
2013-09-19 17:47 ` Ben Widawsky [this message]
2013-09-19 18:01 ` [PATCH] [v2] " Ben Widawsky
2013-09-19 18:41 ` Daniel Vetter
2013-09-19 19:59 ` Ben Widawsky
2013-09-18 4:12 ` [PATCH 07/14] intel_l3_parity: Fix indentation Ben Widawsky
2013-09-18 4:12 ` [PATCH 08/14] intel_l3_parity: Assert all GEN7+ support Ben Widawsky
2013-09-18 4:12 ` [PATCH 09/14] intel_l3_parity: Use getopt for the l3 parity tool Ben Widawsky
2013-09-18 4:12 ` [PATCH 10/14] intel_l3_parity: Hardware info argument Ben Widawsky
2013-09-18 4:12 ` [PATCH 11/14] intel_l3_parity: slice support Ben Widawsky
2013-09-18 4:12 ` [PATCH 12/14] intel_l3_parity: Actually support multiple slices Ben Widawsky
2013-09-18 4:12 ` [PATCH 13/14] intel_l3_parity: Support error injection Ben Widawsky
2013-09-18 4:12 ` [PATCH 14/14] intel_l3_parity: Support a daemonic mode Ben Widawsky
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