From: Paulo Zanoni <przanoni@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 0/4] Haswell modeset fixes
Date: Thu, 19 Sep 2013 17:00:34 -0300 [thread overview]
Message-ID: <1379620838-1491-1-git-send-email-przanoni@gmail.com> (raw)
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Hi
After we solved the Haswell modeset hang, I started to see FIFO underruns. This
series addresses the problems I was able to spot and fix. I think these patches
may help solving the corruptions Linus reported.
Thanks,
Paulo
Paulo Zanoni (3):
drm/i915: promote FIFO underruns to DRM_ERROR
drm/i915: don't disable ERR_INT on the IRQ handler
drm/i915: implement the Haswell mode set sequence workaround
Ville Syrjälä (1):
drm/i915: Disable/enable planes as the first/last thing during modeset
on HSW
drivers/gpu/drm/i915/i915_irq.c | 63 ++++++++--------------
drivers/gpu/drm/i915/intel_display.c | 100 ++++++++++++++++++++++++++---------
2 files changed, 98 insertions(+), 65 deletions(-)
--
1.8.3.1
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next reply other threads:[~2013-09-19 20:00 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-19 20:00 Paulo Zanoni [this message]
2013-09-19 20:00 ` [PATCH 1/4] drm/i915: promote FIFO underruns to DRM_ERROR Paulo Zanoni
2013-09-19 20:16 ` Chris Wilson
2013-09-19 20:20 ` Paulo Zanoni
2013-09-19 20:27 ` Chris Wilson
2013-09-20 6:32 ` Ville Syrjälä
2013-09-20 18:38 ` Paulo Zanoni
2013-09-19 20:00 ` [PATCH 2/4] drm/i915: don't disable ERR_INT on the IRQ handler Paulo Zanoni
2013-09-19 20:18 ` Chris Wilson
2013-09-20 8:08 ` Daniel Vetter
2013-09-19 20:00 ` [PATCH 3/4] drm/i915: Disable/enable planes as the first/last thing during modeset on HSW Paulo Zanoni
2013-09-19 20:00 ` [PATCH 4/4] drm/i915: implement the Haswell mode set sequence workaround Paulo Zanoni
2013-09-20 6:29 ` Ville Syrjälä
2013-09-20 19:21 ` Paulo Zanoni
2013-10-01 19:24 ` Daniel Vetter
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