From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 2/4] drm/i915: don't intel_wait_for_vblank inside intel_enable_pipe Date: Thu, 19 Sep 2013 17:07:27 -0300 Message-ID: <1379621249-1816-3-git-send-email-przanoni@gmail.com> References: <1379621249-1816-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ye0-f174.google.com (mail-ye0-f174.google.com [209.85.213.174]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F3F9E7AD6 for ; Thu, 19 Sep 2013 13:07:49 -0700 (PDT) Received: by mail-ye0-f174.google.com with SMTP id q4so3559732yen.5 for ; Thu, 19 Sep 2013 13:07:49 -0700 (PDT) In-Reply-To: <1379621249-1816-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni Depending on the Gen and encoder, the pipe won't really start after we enable PIPECONF, so waiting for the vblank inside intel_enable_pipe doesn't really make sense for these cases. This patch removes the vblank wait from intel_enable_pipe, but adds vblank waiting code after each call to intel_enable_pipe, so we'll still have the "useless" vblank waits. Future patches will properly deal with each of the vblank waits. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5f1399d..2f546f7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1694,8 +1694,6 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) * * @pipe should be %PIPE_A or %PIPE_B. * - * Will wait until the pipe is actually running (i.e. first vblank) before - * returning. */ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool pch_port, bool dsi) @@ -1741,7 +1739,6 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, return; I915_WRITE(reg, val | PIPECONF_ENABLE); - intel_wait_for_vblank(dev_priv->dev, pipe); } /** @@ -3327,6 +3324,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) intel_update_watermarks(crtc); intel_enable_pipe(dev_priv, pipe, intel_crtc->config.has_pch_encoder, false); + intel_wait_for_vblank(dev, pipe); intel_enable_plane(dev_priv, plane, pipe); intel_enable_planes(crtc); intel_crtc_update_cursor(crtc, true); @@ -3511,6 +3509,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_update_watermarks(crtc); intel_enable_pipe(dev_priv, pipe, intel_crtc->config.has_pch_encoder, false); + intel_wait_for_vblank(dev, pipe); if (intel_crtc->config.has_pch_encoder) lpt_pch_enable(crtc); @@ -3784,6 +3783,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) intel_update_watermarks(crtc); intel_enable_pipe(dev_priv, pipe, false, is_dsi); + intel_wait_for_vblank(dev, pipe); intel_enable_plane(dev_priv, plane, pipe); intel_enable_planes(crtc); intel_crtc_update_cursor(crtc, true); @@ -3822,6 +3822,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) intel_update_watermarks(crtc); intel_enable_pipe(dev_priv, pipe, false, false); + intel_wait_for_vblank(dev, pipe); intel_enable_plane(dev_priv, plane, pipe); intel_enable_planes(crtc); /* The fixup needs to happen before cursor is enabled */ -- 1.8.3.1