From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 4/4] drm/i915: implement the Haswell mode set sequence workaround Date: Fri, 20 Sep 2013 16:21:19 -0300 Message-ID: <1379704879-1635-1-git-send-email-przanoni@gmail.com> References: <20130920062949.GJ4531@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ye0-f175.google.com (mail-ye0-f175.google.com [209.85.213.175]) by gabe.freedesktop.org (Postfix) with ESMTP id BB968E5C0E for ; Fri, 20 Sep 2013 12:21:30 -0700 (PDT) Received: by mail-ye0-f175.google.com with SMTP id q8so287336yen.6 for ; Fri, 20 Sep 2013 12:21:30 -0700 (PDT) In-Reply-To: <20130920062949.GJ4531@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni This workaround is described in the mode set sequence documentation. When enabling planes for the second pipe, we need to wait for 2 vblanks on the first pipe. This should solve "a flash of screen corruption if planes are enabled on second/third pipe during the time that big FIFO mode is exiting". Watermarks are fun :) v2: Save indentation levels Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d8325dd..61621ce 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3441,6 +3441,35 @@ static void haswell_crtc_disable_planes(struct drm_crtc *crtc) intel_disable_plane(dev_priv, plane, pipe); } +/* + * This implements the workaround described in the "notes" section of the mode + * set sequence documentation. When going from no pipes or single pipe to + * multiple pipes, and planes are enabled after the pipe, we need to wait at + * least 2 vblanks on the first pipe before enabling planes on the second pipe. + */ +static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) +{ + struct drm_device *dev = crtc->base.dev; + struct intel_crtc *crtc_it, *other_active_crtc = NULL; + + /* We want to get the other_active_crtc only if there's only 1 other + * active crtc. */ + list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) { + if (!crtc_it->active || crtc_it == crtc) + continue; + + if (other_active_crtc) + return; + + other_active_crtc = crtc_it; + } + if (!other_active_crtc) + return; + + intel_wait_for_vblank(dev, other_active_crtc->pipe); + intel_wait_for_vblank(dev, other_active_crtc->pipe); +} + static void haswell_crtc_enable(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; @@ -3492,6 +3521,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_opregion_notify_encoder(encoder, true); } + /* If we change the relative order between pipe/planes enabling, we need + * to change the workaround. */ + haswell_mode_set_planes_workaround(intel_crtc); haswell_crtc_enable_planes(crtc); /* -- 1.8.3.1