* [PATCH] drm/i915: Clean up the ring scaling calculations
@ 2013-10-01 19:53 Ben Widawsky
2013-10-01 22:32 ` [PATCH] [v2] " Ben Widawsky
0 siblings, 1 reply; 7+ messages in thread
From: Ben Widawsky @ 2013-10-01 19:53 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky, Ben Widawsky
This patch attempts to clean up the ring/IA scaling programming in the
following ways.
1. Fix the comment about the DDR frequency. The math is 266MHz, not
133MHz. Formula was right, docs are wrong.
2. Mask the DCLK register since I don't know how it is defined on future
platforms.
3. use mult_frac instead of magic math.
The patches should yield no difference in the end.
This helps for future platform enabling.
CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/intel_pm.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 698257c..859a419 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3663,9 +3663,9 @@ void gen6_update_ring_freq(struct drm_device *dev)
/* Convert from kHz to MHz */
max_ia_freq /= 1000;
- min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
- /* convert DDR frequency from units of 133.3MHz to bandwidth */
- min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
+ min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
+ /* convert DDR frequency from units of 266.6MHz to bandwidth */
+ min_ring_freq = (min_ring_freq, 2, 3);
/*
* For each potential GPU frequency, load a ring frequency we'd like
@@ -3678,7 +3678,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
unsigned int ia_freq = 0, ring_freq = 0;
if (IS_HASWELL(dev)) {
- ring_freq = (gpu_freq * 5 + 3) / 4;
+ ring_freq = mult_frac(ring_freq, 1, 3);
ring_freq = max(min_ring_freq, ring_freq);
/* leave ia_freq as the default, chosen by cpufreq */
} else {
--
1.8.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH] [v2] drm/i915: Clean up the ring scaling calculations
2013-10-01 19:53 [PATCH] drm/i915: Clean up the ring scaling calculations Ben Widawsky
@ 2013-10-01 22:32 ` Ben Widawsky
2013-10-02 16:19 ` Jesse Barnes
2013-10-02 16:25 ` [PATCH] [v3] " Ben Widawsky
0 siblings, 2 replies; 7+ messages in thread
From: Ben Widawsky @ 2013-10-01 22:32 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky, Ben Widawsky
This patch attempts to clean up the ring/IA scaling programming in the
following ways.
1. Fix the comment about the DDR frequency. The math is 266MHz, not
133MHz. Formula was right, docs are wrong.
2. Mask the DCLK register since I don't know how it is defined on future
platforms.
3. use mult_frac instead of magic math.
This helps for future platform enabling.
v2: Actually use the right patch. The v1 was a mix of things, none of
which was right. Note that due to rounding, we actually get different
values (slightly higher) for the effective ring frequency.
CC: Jesse Barnes <jbarnes@virtuousgeek.org>
CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/intel_pm.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 698257c..cb0876b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3663,9 +3663,9 @@ void gen6_update_ring_freq(struct drm_device *dev)
/* Convert from kHz to MHz */
max_ia_freq /= 1000;
- min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
- /* convert DDR frequency from units of 133.3MHz to bandwidth */
- min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
+ min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
+ /* convert DDR frequency from units of 266.6MHz to bandwidth */
+ min_ring_freq = mult_frac(min_ring_freq, 8, 3);
/*
* For each potential GPU frequency, load a ring frequency we'd like
@@ -3678,7 +3678,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
unsigned int ia_freq = 0, ring_freq = 0;
if (IS_HASWELL(dev)) {
- ring_freq = (gpu_freq * 5 + 3) / 4;
+ ring_freq = mult_frac(gpu_freq, 4, 3);
ring_freq = max(min_ring_freq, ring_freq);
/* leave ia_freq as the default, chosen by cpufreq */
} else {
--
1.8.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH] [v2] drm/i915: Clean up the ring scaling calculations
2013-10-01 22:32 ` [PATCH] [v2] " Ben Widawsky
@ 2013-10-02 16:19 ` Jesse Barnes
2013-10-02 16:25 ` [PATCH] [v3] " Ben Widawsky
1 sibling, 0 replies; 7+ messages in thread
From: Jesse Barnes @ 2013-10-02 16:19 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel GFX, Ben Widawsky
On Tue, 1 Oct 2013 15:32:38 -0700
Ben Widawsky <benjamin.widawsky@intel.com> wrote:
> This patch attempts to clean up the ring/IA scaling programming in the
> following ways.
> 1. Fix the comment about the DDR frequency. The math is 266MHz, not
> 133MHz. Formula was right, docs are wrong.
>
> 2. Mask the DCLK register since I don't know how it is defined on future
> platforms.
>
> 3. use mult_frac instead of magic math.
>
> This helps for future platform enabling.
>
> v2: Actually use the right patch. The v1 was a mix of things, none of
> which was right. Note that due to rounding, we actually get different
> values (slightly higher) for the effective ring frequency.
>
> CC: Jesse Barnes <jbarnes@virtuousgeek.org>
> CC: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 698257c..cb0876b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3663,9 +3663,9 @@ void gen6_update_ring_freq(struct drm_device *dev)
> /* Convert from kHz to MHz */
> max_ia_freq /= 1000;
>
> - min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
> - /* convert DDR frequency from units of 133.3MHz to bandwidth */
> - min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
> + min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
> + /* convert DDR frequency from units of 266.6MHz to bandwidth */
> + min_ring_freq = mult_frac(min_ring_freq, 8, 3);
>
> /*
> * For each potential GPU frequency, load a ring frequency we'd like
> @@ -3678,7 +3678,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
> unsigned int ia_freq = 0, ring_freq = 0;
>
> if (IS_HASWELL(dev)) {
> - ring_freq = (gpu_freq * 5 + 3) / 4;
> + ring_freq = mult_frac(gpu_freq, 4, 3);
> ring_freq = max(min_ring_freq, ring_freq);
> /* leave ia_freq as the default, chosen by cpufreq */
> } else {
Seems like the second mult_frac should be 5,4 rather than 4,3, to
match the original calculation?
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH] [v3] drm/i915: Clean up the ring scaling calculations
2013-10-01 22:32 ` [PATCH] [v2] " Ben Widawsky
2013-10-02 16:19 ` Jesse Barnes
@ 2013-10-02 16:25 ` Ben Widawsky
2013-10-02 16:36 ` Jesse Barnes
2013-10-02 17:05 ` Chris Wilson
1 sibling, 2 replies; 7+ messages in thread
From: Ben Widawsky @ 2013-10-02 16:25 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky, Ben Widawsky
This patch attempts to clean up the ring/IA scaling programming in the
following ways.
1. Fix the comment about the DDR frequency. The math is 266MHz, not
133MHz. Formula was right, docs are wrong.
2. Mask the DCLK register since I don't know how it is defined on future
platforms.
3. use mult_frac instead of magic math.
This helps for future platform enabling.
v2: Actually use the right patch. The v1 was a mix of things, none of
which was right. Note that due to rounding, we actually get different
values (slightly higher) for the effective ring frequency.
v3: Use 1.25 instead of 1.33 as the original code did. (Jesse)
CC: Jesse Barnes <jbarnes@virtuousgeek.org>
CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/intel_pm.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 698257c..9753bd9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3663,9 +3663,9 @@ void gen6_update_ring_freq(struct drm_device *dev)
/* Convert from kHz to MHz */
max_ia_freq /= 1000;
- min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
- /* convert DDR frequency from units of 133.3MHz to bandwidth */
- min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
+ min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
+ /* convert DDR frequency from units of 266.6MHz to bandwidth */
+ min_ring_freq = mult_frac(min_ring_freq, 8, 3);
/*
* For each potential GPU frequency, load a ring frequency we'd like
@@ -3678,7 +3678,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
unsigned int ia_freq = 0, ring_freq = 0;
if (IS_HASWELL(dev)) {
- ring_freq = (gpu_freq * 5 + 3) / 4;
+ ring_freq = mult_frac(gpu_freq, 5, 4);
ring_freq = max(min_ring_freq, ring_freq);
/* leave ia_freq as the default, chosen by cpufreq */
} else {
--
1.8.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH] [v3] drm/i915: Clean up the ring scaling calculations
2013-10-02 16:25 ` [PATCH] [v3] " Ben Widawsky
@ 2013-10-02 16:36 ` Jesse Barnes
2013-10-02 16:56 ` Daniel Vetter
2013-10-02 17:05 ` Chris Wilson
1 sibling, 1 reply; 7+ messages in thread
From: Jesse Barnes @ 2013-10-02 16:36 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel GFX, Ben Widawsky
On Wed, 2 Oct 2013 09:25:02 -0700
Ben Widawsky <benjamin.widawsky@intel.com> wrote:
> This patch attempts to clean up the ring/IA scaling programming in the
> following ways.
> 1. Fix the comment about the DDR frequency. The math is 266MHz, not
> 133MHz. Formula was right, docs are wrong.
>
> 2. Mask the DCLK register since I don't know how it is defined on future
> platforms.
>
> 3. use mult_frac instead of magic math.
>
> This helps for future platform enabling.
>
> v2: Actually use the right patch. The v1 was a mix of things, none of
> which was right. Note that due to rounding, we actually get different
> values (slightly higher) for the effective ring frequency.
>
> v3: Use 1.25 instead of 1.33 as the original code did. (Jesse)
>
> CC: Jesse Barnes <jbarnes@virtuousgeek.org>
> CC: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 698257c..9753bd9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3663,9 +3663,9 @@ void gen6_update_ring_freq(struct drm_device *dev)
> /* Convert from kHz to MHz */
> max_ia_freq /= 1000;
>
> - min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
> - /* convert DDR frequency from units of 133.3MHz to bandwidth */
> - min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
> + min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
> + /* convert DDR frequency from units of 266.6MHz to bandwidth */
> + min_ring_freq = mult_frac(min_ring_freq, 8, 3);
>
> /*
> * For each potential GPU frequency, load a ring frequency we'd like
> @@ -3678,7 +3678,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
> unsigned int ia_freq = 0, ring_freq = 0;
>
> if (IS_HASWELL(dev)) {
> - ring_freq = (gpu_freq * 5 + 3) / 4;
> + ring_freq = mult_frac(gpu_freq, 5, 4);
> ring_freq = max(min_ring_freq, ring_freq);
> /* leave ia_freq as the default, chosen by cpufreq */
> } else {
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] [v3] drm/i915: Clean up the ring scaling calculations
2013-10-02 16:36 ` Jesse Barnes
@ 2013-10-02 16:56 ` Daniel Vetter
0 siblings, 0 replies; 7+ messages in thread
From: Daniel Vetter @ 2013-10-02 16:56 UTC (permalink / raw)
To: Jesse Barnes; +Cc: Intel GFX, Ben Widawsky, Ben Widawsky
On Wed, Oct 02, 2013 at 09:36:04AM -0700, Jesse Barnes wrote:
> On Wed, 2 Oct 2013 09:25:02 -0700
> Ben Widawsky <benjamin.widawsky@intel.com> wrote:
>
> > This patch attempts to clean up the ring/IA scaling programming in the
> > following ways.
> > 1. Fix the comment about the DDR frequency. The math is 266MHz, not
> > 133MHz. Formula was right, docs are wrong.
> >
> > 2. Mask the DCLK register since I don't know how it is defined on future
> > platforms.
> >
> > 3. use mult_frac instead of magic math.
> >
> > This helps for future platform enabling.
> >
> > v2: Actually use the right patch. The v1 was a mix of things, none of
> > which was right. Note that due to rounding, we actually get different
> > values (slightly higher) for the effective ring frequency.
> >
> > v3: Use 1.25 instead of 1.33 as the original code did. (Jesse)
> >
> > CC: Jesse Barnes <jbarnes@virtuousgeek.org>
> > CC: Chris Wilson <chris@chris-wilson.co.uk>
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 698257c..9753bd9 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3663,9 +3663,9 @@ void gen6_update_ring_freq(struct drm_device *dev)
> > /* Convert from kHz to MHz */
> > max_ia_freq /= 1000;
> >
> > - min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
> > - /* convert DDR frequency from units of 133.3MHz to bandwidth */
> > - min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
> > + min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
> > + /* convert DDR frequency from units of 266.6MHz to bandwidth */
> > + min_ring_freq = mult_frac(min_ring_freq, 8, 3);
> >
> > /*
> > * For each potential GPU frequency, load a ring frequency we'd like
> > @@ -3678,7 +3678,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
> > unsigned int ia_freq = 0, ring_freq = 0;
> >
> > if (IS_HASWELL(dev)) {
> > - ring_freq = (gpu_freq * 5 + 3) / 4;
> > + ring_freq = mult_frac(gpu_freq, 5, 4);
> > ring_freq = max(min_ring_freq, ring_freq);
> > /* leave ia_freq as the default, chosen by cpufreq */
> > } else {
>
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] [v3] drm/i915: Clean up the ring scaling calculations
2013-10-02 16:25 ` [PATCH] [v3] " Ben Widawsky
2013-10-02 16:36 ` Jesse Barnes
@ 2013-10-02 17:05 ` Chris Wilson
1 sibling, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2013-10-02 17:05 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel GFX, Ben Widawsky
On Wed, Oct 02, 2013 at 09:25:02AM -0700, Ben Widawsky wrote:
> This patch attempts to clean up the ring/IA scaling programming in the
> following ways.
> 1. Fix the comment about the DDR frequency. The math is 266MHz, not
> 133MHz. Formula was right, docs are wrong.
Confirmed by inspection, units are 266MHz.
> 2. Mask the DCLK register since I don't know how it is defined on future
> platforms.
>
> 3. use mult_frac instead of magic math.
>
> This helps for future platform enabling.
>
> v2: Actually use the right patch. The v1 was a mix of things, none of
> which was right. Note that due to rounding, we actually get different
> values (slightly higher) for the effective ring frequency.
>
> v3: Use 1.25 instead of 1.33 as the original code did. (Jesse)
>
> CC: Jesse Barnes <jbarnes@virtuousgeek.org>
> CC: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 698257c..9753bd9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3663,9 +3663,9 @@ void gen6_update_ring_freq(struct drm_device *dev)
> /* Convert from kHz to MHz */
> max_ia_freq /= 1000;
>
> - min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
> - /* convert DDR frequency from units of 133.3MHz to bandwidth */
> - min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
> + min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
> + /* convert DDR frequency from units of 266.6MHz to bandwidth */
> + min_ring_freq = mult_frac(min_ring_freq, 8, 3);
mult_frac() does not round upwards, so that will be a potential, but
small, difference.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2013-10-02 17:05 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2013-10-01 19:53 [PATCH] drm/i915: Clean up the ring scaling calculations Ben Widawsky
2013-10-01 22:32 ` [PATCH] [v2] " Ben Widawsky
2013-10-02 16:19 ` Jesse Barnes
2013-10-02 16:25 ` [PATCH] [v3] " Ben Widawsky
2013-10-02 16:36 ` Jesse Barnes
2013-10-02 16:56 ` Daniel Vetter
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