* [PATCH v2 1/2] drm/i915: pass mode to ELD write vfuncs
[not found] <id:cover.1381765995.git.jani.nikula@intel.com>
@ 2013-10-16 9:34 ` Jani Nikula
2013-10-16 9:34 ` [PATCH v2 2/2] drm/i915: set HDMI pixel clock in audio configuration Jani Nikula
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Jani Nikula @ 2013-10-16 9:34 UTC (permalink / raw)
To: intel-gfx, David Härdeman, Jasper Smet; +Cc: jani.nikula
This will be needed for setting the HDMI pixel clock for audio
config. No functional changes.
v2: Now with a commit message.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_display.c | 11 +++++++----
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6106d3d..caee590 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -379,7 +379,8 @@ struct drm_i915_display_funcs {
void (*crtc_disable)(struct drm_crtc *crtc);
void (*off)(struct drm_crtc *crtc);
void (*write_eld)(struct drm_connector *connector,
- struct drm_crtc *crtc);
+ struct drm_crtc *crtc,
+ struct drm_display_mode *mode);
void (*fdi_link_train)(struct drm_crtc *crtc);
void (*init_clock_gating)(struct drm_device *dev);
int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4f1b636..55740f2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6752,7 +6752,8 @@ static bool intel_eld_uptodate(struct drm_connector *connector,
}
static void g4x_write_eld(struct drm_connector *connector,
- struct drm_crtc *crtc)
+ struct drm_crtc *crtc,
+ struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv = connector->dev->dev_private;
uint8_t *eld = connector->eld;
@@ -6792,7 +6793,8 @@ static void g4x_write_eld(struct drm_connector *connector,
}
static void haswell_write_eld(struct drm_connector *connector,
- struct drm_crtc *crtc)
+ struct drm_crtc *crtc,
+ struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv = connector->dev->dev_private;
uint8_t *eld = connector->eld;
@@ -6879,7 +6881,8 @@ static void haswell_write_eld(struct drm_connector *connector,
}
static void ironlake_write_eld(struct drm_connector *connector,
- struct drm_crtc *crtc)
+ struct drm_crtc *crtc,
+ struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv = connector->dev->dev_private;
uint8_t *eld = connector->eld;
@@ -6974,7 +6977,7 @@ void intel_write_eld(struct drm_encoder *encoder,
connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
if (dev_priv->display.write_eld)
- dev_priv->display.write_eld(connector, crtc);
+ dev_priv->display.write_eld(connector, crtc, mode);
}
static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 2/2] drm/i915: set HDMI pixel clock in audio configuration
2013-10-16 9:34 ` [PATCH v2 1/2] drm/i915: pass mode to ELD write vfuncs Jani Nikula
@ 2013-10-16 9:34 ` Jani Nikula
2013-10-17 12:01 ` Rodrigo Vivi
2013-10-24 9:07 ` Jasper Smet
2013-10-16 9:38 ` [PATCH v2 1/2] drm/i915: pass mode to ELD write vfuncs Jani Nikula
2013-10-17 12:02 ` Rodrigo Vivi
2 siblings, 2 replies; 9+ messages in thread
From: Jani Nikula @ 2013-10-16 9:34 UTC (permalink / raw)
To: intel-gfx, David Härdeman, Jasper Smet; +Cc: jani.nikula
The HDMI audio expects HDMI pixel clock to be set in the audio
configuration. We've currently just set 0, using 25.2 / 1.001 kHz
frequency, which fails with some modes.
v2: Now with a commit message.
Reference: http://mid.gmane.org/CAGpEb3Ep1LRZETPxHGRfBDqr5Ts2tAc8gCukWwugUf1U5NYv1g@mail.gmail.com
Reference: http://mid.gmane.org/20130206213533.GA16367@hardeman.nu
Reported-by: David Härdeman <david@hardeman.nu>
Reported-by: Jasper Smet <josbeir@gmail.com>
Tested-by: Jasper Smet <josbeir@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++-
drivers/gpu/drm/i915/intel_display.c | 48 +++++++++++++++++++++++++++++++---
2 files changed, 55 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 13153c3..3266819 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4875,7 +4875,17 @@
#define AUD_CONFIG_LOWER_N_SHIFT 4
#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
-#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
/* HSW Audio */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 55740f2..a097f84 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6722,6 +6722,44 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
return 0;
}
+static struct {
+ int clock;
+ u32 config;
+} hdmi_audio_clock[] = {
+ { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
+ { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
+ { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
+ { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
+ { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
+ { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
+ { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
+ { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
+ { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
+ { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
+};
+
+/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
+static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
+ if (mode->clock == hdmi_audio_clock[i].clock)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(hdmi_audio_clock)) {
+ DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
+ i = 1;
+ }
+
+ DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
+ hdmi_audio_clock[i].clock,
+ hdmi_audio_clock[i].config);
+
+ return hdmi_audio_clock[i].config;
+}
+
static bool intel_eld_uptodate(struct drm_connector *connector,
int reg_eldv, uint32_t bits_eldv,
int reg_elda, uint32_t bits_elda,
@@ -6847,8 +6885,9 @@ static void haswell_write_eld(struct drm_connector *connector,
DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
- } else
- I915_WRITE(aud_config, 0);
+ } else {
+ I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
+ }
if (intel_eld_uptodate(connector,
aud_cntrl_st2, eldv,
@@ -6926,8 +6965,9 @@ static void ironlake_write_eld(struct drm_connector *connector,
DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
- } else
- I915_WRITE(aud_config, 0);
+ } else {
+ I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
+ }
if (intel_eld_uptodate(connector,
aud_cntrl_st2, eldv,
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] drm/i915: pass mode to ELD write vfuncs
2013-10-16 9:34 ` [PATCH v2 1/2] drm/i915: pass mode to ELD write vfuncs Jani Nikula
2013-10-16 9:34 ` [PATCH v2 2/2] drm/i915: set HDMI pixel clock in audio configuration Jani Nikula
@ 2013-10-16 9:38 ` Jani Nikula
2013-10-17 12:02 ` Rodrigo Vivi
2 siblings, 0 replies; 9+ messages in thread
From: Jani Nikula @ 2013-10-16 9:38 UTC (permalink / raw)
To: intel-gfx, David Härdeman, Jasper Smet, Lin, Mengdong
Mengdong, I meant to CC you on these two patches. Please have a look.
I also screwed up in-reply-to, was meant to be
http://mid.gmane.org/cover.1381765995.git.jani.nikula@intel.com
BR,
Jani.
On Wed, 16 Oct 2013, Jani Nikula <jani.nikula@intel.com> wrote:
> This will be needed for setting the HDMI pixel clock for audio
> config. No functional changes.
>
> v2: Now with a commit message.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 ++-
> drivers/gpu/drm/i915/intel_display.c | 11 +++++++----
> 2 files changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6106d3d..caee590 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -379,7 +379,8 @@ struct drm_i915_display_funcs {
> void (*crtc_disable)(struct drm_crtc *crtc);
> void (*off)(struct drm_crtc *crtc);
> void (*write_eld)(struct drm_connector *connector,
> - struct drm_crtc *crtc);
> + struct drm_crtc *crtc,
> + struct drm_display_mode *mode);
> void (*fdi_link_train)(struct drm_crtc *crtc);
> void (*init_clock_gating)(struct drm_device *dev);
> int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4f1b636..55740f2 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6752,7 +6752,8 @@ static bool intel_eld_uptodate(struct drm_connector *connector,
> }
>
> static void g4x_write_eld(struct drm_connector *connector,
> - struct drm_crtc *crtc)
> + struct drm_crtc *crtc,
> + struct drm_display_mode *mode)
> {
> struct drm_i915_private *dev_priv = connector->dev->dev_private;
> uint8_t *eld = connector->eld;
> @@ -6792,7 +6793,8 @@ static void g4x_write_eld(struct drm_connector *connector,
> }
>
> static void haswell_write_eld(struct drm_connector *connector,
> - struct drm_crtc *crtc)
> + struct drm_crtc *crtc,
> + struct drm_display_mode *mode)
> {
> struct drm_i915_private *dev_priv = connector->dev->dev_private;
> uint8_t *eld = connector->eld;
> @@ -6879,7 +6881,8 @@ static void haswell_write_eld(struct drm_connector *connector,
> }
>
> static void ironlake_write_eld(struct drm_connector *connector,
> - struct drm_crtc *crtc)
> + struct drm_crtc *crtc,
> + struct drm_display_mode *mode)
> {
> struct drm_i915_private *dev_priv = connector->dev->dev_private;
> uint8_t *eld = connector->eld;
> @@ -6974,7 +6977,7 @@ void intel_write_eld(struct drm_encoder *encoder,
> connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
>
> if (dev_priv->display.write_eld)
> - dev_priv->display.write_eld(connector, crtc);
> + dev_priv->display.write_eld(connector, crtc, mode);
> }
>
> static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/2] drm/i915: set HDMI pixel clock in audio configuration
2013-10-16 9:34 ` [PATCH v2 2/2] drm/i915: set HDMI pixel clock in audio configuration Jani Nikula
@ 2013-10-17 12:01 ` Rodrigo Vivi
2013-10-17 12:40 ` Daniel Vetter
2013-10-24 9:07 ` Jasper Smet
1 sibling, 1 reply; 9+ messages in thread
From: Rodrigo Vivi @ 2013-10-17 12:01 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
On Wed, Oct 16, 2013 at 6:34 AM, Jani Nikula <jani.nikula@intel.com> wrote:
> The HDMI audio expects HDMI pixel clock to be set in the audio
> configuration. We've currently just set 0, using 25.2 / 1.001 kHz
> frequency, which fails with some modes.
>
> v2: Now with a commit message.
>
> Reference: http://mid.gmane.org/CAGpEb3Ep1LRZETPxHGRfBDqr5Ts2tAc8gCukWwugUf1U5NYv1g@mail.gmail.com
> Reference: http://mid.gmane.org/20130206213533.GA16367@hardeman.nu
> Reported-by: David Härdeman <david@hardeman.nu>
> Reported-by: Jasper Smet <josbeir@gmail.com>
> Tested-by: Jasper Smet <josbeir@gmail.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++-
> drivers/gpu/drm/i915/intel_display.c | 48 +++++++++++++++++++++++++++++++---
> 2 files changed, 55 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 13153c3..3266819 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4875,7 +4875,17 @@
> #define AUD_CONFIG_LOWER_N_SHIFT 4
> #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
> #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
> #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
>
> /* HSW Audio */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 55740f2..a097f84 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6722,6 +6722,44 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
> return 0;
> }
>
> +static struct {
> + int clock;
> + u32 config;
> +} hdmi_audio_clock[] = {
> + { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
> + { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
> + { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
> + { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
> + { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
> + { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
> + { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
> + { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
> + { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
> + { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
> +};
> +
> +/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
> +static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
> + if (mode->clock == hdmi_audio_clock[i].clock)
> + break;
> + }
> +
> + if (i == ARRAY_SIZE(hdmi_audio_clock)) {
> + DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
> + i = 1;
> + }
> +
> + DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
> + hdmi_audio_clock[i].clock,
> + hdmi_audio_clock[i].config);
> +
> + return hdmi_audio_clock[i].config;
> +}
> +
> static bool intel_eld_uptodate(struct drm_connector *connector,
> int reg_eldv, uint32_t bits_eldv,
> int reg_elda, uint32_t bits_elda,
> @@ -6847,8 +6885,9 @@ static void haswell_write_eld(struct drm_connector *connector,
> DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
> eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
> I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
> - } else
> - I915_WRITE(aud_config, 0);
> + } else {
> + I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
> + }
>
> if (intel_eld_uptodate(connector,
> aud_cntrl_st2, eldv,
> @@ -6926,8 +6965,9 @@ static void ironlake_write_eld(struct drm_connector *connector,
> DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
> eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
> I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
> - } else
> - I915_WRITE(aud_config, 0);
> + } else {
> + I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
> + }
>
> if (intel_eld_uptodate(connector,
> aud_cntrl_st2, eldv,
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] drm/i915: pass mode to ELD write vfuncs
2013-10-16 9:34 ` [PATCH v2 1/2] drm/i915: pass mode to ELD write vfuncs Jani Nikula
2013-10-16 9:34 ` [PATCH v2 2/2] drm/i915: set HDMI pixel clock in audio configuration Jani Nikula
2013-10-16 9:38 ` [PATCH v2 1/2] drm/i915: pass mode to ELD write vfuncs Jani Nikula
@ 2013-10-17 12:02 ` Rodrigo Vivi
2 siblings, 0 replies; 9+ messages in thread
From: Rodrigo Vivi @ 2013-10-17 12:02 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
On Wed, Oct 16, 2013 at 6:34 AM, Jani Nikula <jani.nikula@intel.com> wrote:
> This will be needed for setting the HDMI pixel clock for audio
> config. No functional changes.
>
> v2: Now with a commit message.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 ++-
> drivers/gpu/drm/i915/intel_display.c | 11 +++++++----
> 2 files changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6106d3d..caee590 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -379,7 +379,8 @@ struct drm_i915_display_funcs {
> void (*crtc_disable)(struct drm_crtc *crtc);
> void (*off)(struct drm_crtc *crtc);
> void (*write_eld)(struct drm_connector *connector,
> - struct drm_crtc *crtc);
> + struct drm_crtc *crtc,
> + struct drm_display_mode *mode);
> void (*fdi_link_train)(struct drm_crtc *crtc);
> void (*init_clock_gating)(struct drm_device *dev);
> int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4f1b636..55740f2 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6752,7 +6752,8 @@ static bool intel_eld_uptodate(struct drm_connector *connector,
> }
>
> static void g4x_write_eld(struct drm_connector *connector,
> - struct drm_crtc *crtc)
> + struct drm_crtc *crtc,
> + struct drm_display_mode *mode)
> {
> struct drm_i915_private *dev_priv = connector->dev->dev_private;
> uint8_t *eld = connector->eld;
> @@ -6792,7 +6793,8 @@ static void g4x_write_eld(struct drm_connector *connector,
> }
>
> static void haswell_write_eld(struct drm_connector *connector,
> - struct drm_crtc *crtc)
> + struct drm_crtc *crtc,
> + struct drm_display_mode *mode)
> {
> struct drm_i915_private *dev_priv = connector->dev->dev_private;
> uint8_t *eld = connector->eld;
> @@ -6879,7 +6881,8 @@ static void haswell_write_eld(struct drm_connector *connector,
> }
>
> static void ironlake_write_eld(struct drm_connector *connector,
> - struct drm_crtc *crtc)
> + struct drm_crtc *crtc,
> + struct drm_display_mode *mode)
> {
> struct drm_i915_private *dev_priv = connector->dev->dev_private;
> uint8_t *eld = connector->eld;
> @@ -6974,7 +6977,7 @@ void intel_write_eld(struct drm_encoder *encoder,
> connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
>
> if (dev_priv->display.write_eld)
> - dev_priv->display.write_eld(connector, crtc);
> + dev_priv->display.write_eld(connector, crtc, mode);
> }
>
> static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/2] drm/i915: set HDMI pixel clock in audio configuration
2013-10-17 12:01 ` Rodrigo Vivi
@ 2013-10-17 12:40 ` Daniel Vetter
0 siblings, 0 replies; 9+ messages in thread
From: Daniel Vetter @ 2013-10-17 12:40 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Jani Nikula, intel-gfx
On Thu, Oct 17, 2013 at 09:01:52AM -0300, Rodrigo Vivi wrote:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
>
> On Wed, Oct 16, 2013 at 6:34 AM, Jani Nikula <jani.nikula@intel.com> wrote:
> > The HDMI audio expects HDMI pixel clock to be set in the audio
> > configuration. We've currently just set 0, using 25.2 / 1.001 kHz
> > frequency, which fails with some modes.
> >
> > v2: Now with a commit message.
> >
> > Reference: http://mid.gmane.org/CAGpEb3Ep1LRZETPxHGRfBDqr5Ts2tAc8gCukWwugUf1U5NYv1g@mail.gmail.com
> > Reference: http://mid.gmane.org/20130206213533.GA16367@hardeman.nu
> > Reported-by: David Härdeman <david@hardeman.nu>
> > Reported-by: Jasper Smet <josbeir@gmail.com>
> > Tested-by: Jasper Smet <josbeir@gmail.com>
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Both merged, thanks for patches and review.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/2] drm/i915: set HDMI pixel clock in audio configuration
2013-10-16 9:34 ` [PATCH v2 2/2] drm/i915: set HDMI pixel clock in audio configuration Jani Nikula
2013-10-17 12:01 ` Rodrigo Vivi
@ 2013-10-24 9:07 ` Jasper Smet
2013-10-24 9:59 ` David Härdeman
1 sibling, 1 reply; 9+ messages in thread
From: Jasper Smet @ 2013-10-24 9:07 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 6132 bytes --]
Although i know it also happens in windows, the one particular thing i am
'fiddling' with is that when i try the receiver with an nvidia or amd apu
(ion, e-450 trough hdmi) with my pioneer receiver audio works fine with
44100hz at the 1080p@50/60 modes. Only with intel i need to force
upstreaming to 48000hz.
So are we really sure this is a bug with the receiver or still something
wrong with the driver / pixel clock issue?
Is there anything else we i do to help ?
On Wed, Oct 16, 2013 at 11:34 AM, Jani Nikula <jani.nikula@intel.com> wrote:
> The HDMI audio expects HDMI pixel clock to be set in the audio
> configuration. We've currently just set 0, using 25.2 / 1.001 kHz
> frequency, which fails with some modes.
>
> v2: Now with a commit message.
>
> Reference:
> http://mid.gmane.org/CAGpEb3Ep1LRZETPxHGRfBDqr5Ts2tAc8gCukWwugUf1U5NYv1g@mail.gmail.com
> Reference: http://mid.gmane.org/20130206213533.GA16367@hardeman.nu
> Reported-by: David Härdeman <david@hardeman.nu>
> Reported-by: Jasper Smet <josbeir@gmail.com>
> Tested-by: Jasper Smet <josbeir@gmail.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++-
> drivers/gpu/drm/i915/intel_display.c | 48
> +++++++++++++++++++++++++++++++---
> 2 files changed, 55 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 13153c3..3266819 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4875,7 +4875,17 @@
> #define AUD_CONFIG_LOWER_N_SHIFT 4
> #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
> #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
> #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
>
> /* HSW Audio */
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 55740f2..a097f84 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6722,6 +6722,44 @@ static int intel_crtc_mode_set(struct drm_crtc
> *crtc,
> return 0;
> }
>
> +static struct {
> + int clock;
> + u32 config;
> +} hdmi_audio_clock[] = {
> + { DIV_ROUND_UP(25200 * 1000, 1001),
> AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
> + { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec
> */
> + { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
> + { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
> + { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
> + { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
> + { DIV_ROUND_UP(74250 * 1000, 1001),
> AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
> + { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
> + { DIV_ROUND_UP(148500 * 1000, 1001),
> AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
> + { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
> +};
> +
> +/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
> +static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
> + if (mode->clock == hdmi_audio_clock[i].clock)
> + break;
> + }
> +
> + if (i == ARRAY_SIZE(hdmi_audio_clock)) {
> + DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not
> found, falling back to defaults\n", mode->clock);
> + i = 1;
> + }
> +
> + DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d
> (0x%08x)\n",
> + hdmi_audio_clock[i].clock,
> + hdmi_audio_clock[i].config);
> +
> + return hdmi_audio_clock[i].config;
> +}
> +
> static bool intel_eld_uptodate(struct drm_connector *connector,
> int reg_eldv, uint32_t bits_eldv,
> int reg_elda, uint32_t bits_elda,
> @@ -6847,8 +6885,9 @@ static void haswell_write_eld(struct drm_connector
> *connector,
> DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
> eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
> I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 =
> DP */
> - } else
> - I915_WRITE(aud_config, 0);
> + } else {
> + I915_WRITE(aud_config,
> audio_config_hdmi_pixel_clock(mode));
> + }
>
> if (intel_eld_uptodate(connector,
> aud_cntrl_st2, eldv,
> @@ -6926,8 +6965,9 @@ static void ironlake_write_eld(struct drm_connector
> *connector,
> DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
> eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
> I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 =
> DP */
> - } else
> - I915_WRITE(aud_config, 0);
> + } else {
> + I915_WRITE(aud_config,
> audio_config_hdmi_pixel_clock(mode));
> + }
>
> if (intel_eld_uptodate(connector,
> aud_cntrl_st2, eldv,
> --
> 1.7.9.5
>
>
--
Met Vriendelijke Groeten
Jasper Smet
Developer
Twitter: josbeir
E-mail: josbeir@gmail.com
Mobile: 0486/41.75.45
[-- Attachment #1.2: Type: text/html, Size: 7379 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/2] drm/i915: set HDMI pixel clock in audio configuration
2013-10-24 9:07 ` Jasper Smet
@ 2013-10-24 9:59 ` David Härdeman
2013-10-27 12:39 ` Daniel Vetter
0 siblings, 1 reply; 9+ messages in thread
From: David Härdeman @ 2013-10-24 9:59 UTC (permalink / raw)
To: Jasper Smet; +Cc: Jani Nikula, intel-gfx
It should also be noted that manually hard-coding the pixel clock value
to an obviously incorrect value will also cause the Pioneer receiver to
do the right thing (I assume it will ignore the incorrect value and
calculate it on the fly) - that would point towards some kind of bug /
hardware incompatibility in the Pioneer receiver. But I agree that the
receiver *does* work with other hardware that I've tried.
Attempts to contact Pioneer have been fruitless so far. Maybe Intel
would have better luck there...
On 2013-10-24 11:07, Jasper Smet wrote:
> Although i know it also happens in windows, the one particular thing i
> am 'fiddling' with is that when i try the receiver with an nvidia or
> amd apu (ion, e-450 trough hdmi) with my pioneer receiver audio works
> fine with 44100hz at the 1080p@50/60 modes. Only with intel i need to
> force upstreaming to 48000hz.
>
> So are we really sure this is a bug with the receiver or still
> something wrong with the driver / pixel clock issue?
>
> Is there anything else we i do to help ?
>
> On Wed, Oct 16, 2013 at 11:34 AM, Jani Nikula <jani.nikula@intel.com>
> wrote:
>
>> The HDMI audio expects HDMI pixel clock to be set in the audio
>> configuration. We've currently just set 0, using 25.2 / 1.001 kHz
>> frequency, which fails with some modes.
>>
>> v2: Now with a commit message.
>>
>> Reference:
>>
> http://mid.gmane.org/CAGpEb3Ep1LRZETPxHGRfBDqr5Ts2tAc8gCukWwugUf1U5NYv1g@mail.gmail.com
>> [1]
>> Reference: http://mid.gmane.org/20130206213533.GA16367@hardeman.nu
>> Reported-by: David Härdeman <david@hardeman.nu>
>> Reported-by: Jasper Smet <josbeir@gmail.com>
>> Tested-by: Jasper Smet <josbeir@gmail.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++-
>> drivers/gpu/drm/i915/intel_display.c | 48
>> +++++++++++++++++++++++++++++++---
>> 2 files changed, 55 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 13153c3..3266819 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4875,7 +4875,17 @@
>> #define AUD_CONFIG_LOWER_N_SHIFT 4
>> #define AUD_CONFIG_LOWER_N_VALUE (0xfff <<
>> 4)
>> #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
>> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
>> #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
>>
>> /* HSW Audio */
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 55740f2..a097f84 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -6722,6 +6722,44 @@ static int intel_crtc_mode_set(struct
>> drm_crtc *crtc,
>> return 0;
>> }
>>
>> +static struct {
>> + int clock;
>> + u32 config;
>> +} hdmi_audio_clock[] = {
>> + { DIV_ROUND_UP(25200 * 1000, 1001),
>> AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
>> + { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default
>> per bspec */
>> + { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
>> + { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
>> },
>> + { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
>> + { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
>> },
>> + { DIV_ROUND_UP(74250 * 1000, 1001),
>> AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
>> + { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
>> + { DIV_ROUND_UP(148500 * 1000, 1001),
>> AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
>> + { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
>> +};
>> +
>> +/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
>> +static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode
>> *mode)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
>> + if (mode->clock ==
>> hdmi_audio_clock[i].clock)
>> + break;
>> + }
>> +
>> + if (i == ARRAY_SIZE(hdmi_audio_clock)) {
>> + DRM_DEBUG_KMS("HDMI audio pixel clock
>> setting for %d not found, falling back to defaultsn", mode->clock);
>> + i = 1;
>> + }
>> +
>> + DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d
>> (0x%08x)n",
>> + hdmi_audio_clock[i].clock,
>> + hdmi_audio_clock[i].config);
>> +
>> + return hdmi_audio_clock[i].config;
>> +}
>> +
>> static bool intel_eld_uptodate(struct drm_connector *connector,
>> int reg_eldv,
>> uint32_t bits_eldv,
>> int reg_elda,
>> uint32_t bits_elda,
>> @@ -6847,8 +6885,9 @@ static void haswell_write_eld(struct
>> drm_connector *connector,
>> DRM_DEBUG_DRIVER("ELD: DisplayPort
>> detectedn");
>> eld[5] |= (1 << 2); /* Conn_Type, 0x1
>> = DisplayPort */
>> I915_WRITE(aud_config,
>> AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
>> - } else
>> - I915_WRITE(aud_config, 0);
>> + } else {
>> + I915_WRITE(aud_config,
>> audio_config_hdmi_pixel_clock(mode));
>> + }
>>
>> if (intel_eld_uptodate(connector,
>> aud_cntrl_st2, eldv,
>> @@ -6926,8 +6965,9 @@ static void ironlake_write_eld(struct
>> drm_connector *connector,
>> DRM_DEBUG_DRIVER("ELD: DisplayPort
>> detectedn");
>> eld[5] |= (1 << 2); /* Conn_Type, 0x1
>> = DisplayPort */
>> I915_WRITE(aud_config,
>> AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
>> - } else
>> - I915_WRITE(aud_config, 0);
>> + } else {
>> + I915_WRITE(aud_config,
>> audio_config_hdmi_pixel_clock(mode));
>> + }
>>
>> if (intel_eld_uptodate(connector,
>> aud_cntrl_st2, eldv,
>> --
>> 1.7.9.5
>
> --
> Met Vriendelijke Groeten
>
> Jasper Smet
> Developer
>
> Twitter: josbeir
> E-mail: josbeir@gmail.com
> Mobile: 0486/41.75.45
>
> Links:
> ------
> [1]
> http://mid.gmane.org/CAGpEb3Ep1LRZETPxHGRfBDqr5Ts2tAc8gCukWwugUf1U5NYv1g@mail.gmail.com
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/2] drm/i915: set HDMI pixel clock in audio configuration
2013-10-24 9:59 ` David Härdeman
@ 2013-10-27 12:39 ` Daniel Vetter
0 siblings, 0 replies; 9+ messages in thread
From: Daniel Vetter @ 2013-10-27 12:39 UTC (permalink / raw)
To: David Härdeman; +Cc: Jani Nikula, intel-gfx
On Thu, Oct 24, 2013 at 11:59:35AM +0200, David Härdeman wrote:
> It should also be noted that manually hard-coding the pixel clock
> value to an obviously incorrect value will also cause the Pioneer
> receiver to do the right thing (I assume it will ignore the
> incorrect value and calculate it on the fly) - that would point
> towards some kind of bug / hardware incompatibility in the Pioneer
> receiver. But I agree that the receiver *does* work with other
> hardware that I've tried.
>
> Attempts to contact Pioneer have been fruitless so far. Maybe Intel
> would have better luck there...
The hw has shipped, so usually that means you're out of luck. Maybe we
simply needs to start adding eld quirks to EDIDs ...
-Daniel
>
> On 2013-10-24 11:07, Jasper Smet wrote:
> >Although i know it also happens in windows, the one particular thing i
> >am 'fiddling' with is that when i try the receiver with an nvidia or
> >amd apu (ion, e-450 trough hdmi) with my pioneer receiver audio works
> >fine with 44100hz at the 1080p@50/60 modes. Only with intel i need to
> >force upstreaming to 48000hz.
> >
> >So are we really sure this is a bug with the receiver or still
> >something wrong with the driver / pixel clock issue?
> >
> >Is there anything else we i do to help ?
> >
> >On Wed, Oct 16, 2013 at 11:34 AM, Jani Nikula <jani.nikula@intel.com>
> >wrote:
> >
> >>The HDMI audio expects HDMI pixel clock to be set in the audio
> >>configuration. We've currently just set 0, using 25.2 / 1.001 kHz
> >>frequency, which fails with some modes.
> >>
> >>v2: Now with a commit message.
> >>
> >>Reference:
> >>
> >http://mid.gmane.org/CAGpEb3Ep1LRZETPxHGRfBDqr5Ts2tAc8gCukWwugUf1U5NYv1g@mail.gmail.com
> >>[1]
> >>Reference: http://mid.gmane.org/20130206213533.GA16367@hardeman.nu
> >>Reported-by: David Härdeman <david@hardeman.nu>
> >>Reported-by: Jasper Smet <josbeir@gmail.com>
> >>Tested-by: Jasper Smet <josbeir@gmail.com>
> >>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >>---
> >> drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++-
> >> drivers/gpu/drm/i915/intel_display.c | 48
> >>+++++++++++++++++++++++++++++++---
> >> 2 files changed, 55 insertions(+), 5 deletions(-)
> >>
> >>diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >>b/drivers/gpu/drm/i915/i915_reg.h
> >>index 13153c3..3266819 100644
> >>--- a/drivers/gpu/drm/i915/i915_reg.h
> >>+++ b/drivers/gpu/drm/i915/i915_reg.h
> >>@@ -4875,7 +4875,17 @@
> >> #define AUD_CONFIG_LOWER_N_SHIFT 4
> >> #define AUD_CONFIG_LOWER_N_VALUE (0xfff <<
> >>4)
> >> #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
> >>-#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
> >>+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
> >>+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
> >>+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
> >>+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
> >>+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
> >>+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
> >>+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
> >>+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
> >>+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
> >>+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
> >>+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
> >> #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
> >>
> >> /* HSW Audio */
> >>diff --git a/drivers/gpu/drm/i915/intel_display.c
> >>b/drivers/gpu/drm/i915/intel_display.c
> >>index 55740f2..a097f84 100644
> >>--- a/drivers/gpu/drm/i915/intel_display.c
> >>+++ b/drivers/gpu/drm/i915/intel_display.c
> >>@@ -6722,6 +6722,44 @@ static int intel_crtc_mode_set(struct
> >>drm_crtc *crtc,
> >> return 0;
> >> }
> >>
> >>+static struct {
> >>+ int clock;
> >>+ u32 config;
> >>+} hdmi_audio_clock[] = {
> >>+ { DIV_ROUND_UP(25200 * 1000, 1001),
> >>AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
> >>+ { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default
> >>per bspec */
> >>+ { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
> >>+ { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
> >>},
> >>+ { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
> >>+ { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
> >>},
> >>+ { DIV_ROUND_UP(74250 * 1000, 1001),
> >>AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
> >>+ { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
> >>+ { DIV_ROUND_UP(148500 * 1000, 1001),
> >>AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
> >>+ { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
> >>+};
> >>+
> >>+/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
> >>+static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode
> >>*mode)
> >>+{
> >>+ int i;
> >>+
> >>+ for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
> >>+ if (mode->clock ==
> >>hdmi_audio_clock[i].clock)
> >>+ break;
> >>+ }
> >>+
> >>+ if (i == ARRAY_SIZE(hdmi_audio_clock)) {
> >>+ DRM_DEBUG_KMS("HDMI audio pixel clock
> >>setting for %d not found, falling back to defaultsn", mode->clock);
> >>+ i = 1;
> >>+ }
> >>+
> >>+ DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d
> >>(0x%08x)n",
> >>+ hdmi_audio_clock[i].clock,
> >>+ hdmi_audio_clock[i].config);
> >>+
> >>+ return hdmi_audio_clock[i].config;
> >>+}
> >>+
> >> static bool intel_eld_uptodate(struct drm_connector *connector,
> >> int reg_eldv,
> >>uint32_t bits_eldv,
> >> int reg_elda,
> >>uint32_t bits_elda,
> >>@@ -6847,8 +6885,9 @@ static void haswell_write_eld(struct
> >>drm_connector *connector,
> >> DRM_DEBUG_DRIVER("ELD: DisplayPort
> >>detectedn");
> >> eld[5] |= (1 << 2); /* Conn_Type, 0x1
> >>= DisplayPort */
> >> I915_WRITE(aud_config,
> >>AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
> >>- } else
> >>- I915_WRITE(aud_config, 0);
> >>+ } else {
> >>+ I915_WRITE(aud_config,
> >>audio_config_hdmi_pixel_clock(mode));
> >>+ }
> >>
> >> if (intel_eld_uptodate(connector,
> >> aud_cntrl_st2, eldv,
> >>@@ -6926,8 +6965,9 @@ static void ironlake_write_eld(struct
> >>drm_connector *connector,
> >> DRM_DEBUG_DRIVER("ELD: DisplayPort
> >>detectedn");
> >> eld[5] |= (1 << 2); /* Conn_Type, 0x1
> >>= DisplayPort */
> >> I915_WRITE(aud_config,
> >>AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
> >>- } else
> >>- I915_WRITE(aud_config, 0);
> >>+ } else {
> >>+ I915_WRITE(aud_config,
> >>audio_config_hdmi_pixel_clock(mode));
> >>+ }
> >>
> >> if (intel_eld_uptodate(connector,
> >> aud_cntrl_st2, eldv,
> >>--
> >>1.7.9.5
> >
> >--
> >Met Vriendelijke Groeten
> >
> >Jasper Smet
> >Developer
> >
> >Twitter: josbeir
> >E-mail: josbeir@gmail.com
> > Mobile: 0486/41.75.45
> >
> >Links:
> >------
> >[1]
> >http://mid.gmane.org/CAGpEb3Ep1LRZETPxHGRfBDqr5Ts2tAc8gCukWwugUf1U5NYv1g@mail.gmail.com
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2013-10-27 12:39 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
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[not found] <id:cover.1381765995.git.jani.nikula@intel.com>
2013-10-16 9:34 ` [PATCH v2 1/2] drm/i915: pass mode to ELD write vfuncs Jani Nikula
2013-10-16 9:34 ` [PATCH v2 2/2] drm/i915: set HDMI pixel clock in audio configuration Jani Nikula
2013-10-17 12:01 ` Rodrigo Vivi
2013-10-17 12:40 ` Daniel Vetter
2013-10-24 9:07 ` Jasper Smet
2013-10-24 9:59 ` David Härdeman
2013-10-27 12:39 ` Daniel Vetter
2013-10-16 9:38 ` [PATCH v2 1/2] drm/i915: pass mode to ELD write vfuncs Jani Nikula
2013-10-17 12:02 ` Rodrigo Vivi
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