* [PATCH 1/3] drm/i915: add bunit read/write routines
@ 2013-10-28 18:14 Jesse Barnes
2013-10-28 18:14 ` [PATCH 2/3] drm/i915: move VLV DDR freq fetch into init_clock_gating Jesse Barnes
2013-10-28 18:14 ` [PATCH 3/3] drm/i915/vlv: update czclk freq if needed for high bandwidth modes Jesse Barnes
0 siblings, 2 replies; 5+ messages in thread
From: Jesse Barnes @ 2013-10-28 18:14 UTC (permalink / raw)
To: intel-gfx
For modifying self-refresh exit latency.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 16 ++++++++++++++++
3 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 20c409c..4cf7f60 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2356,6 +2356,8 @@ u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
+void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c6cc8e..6a6eb8b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -348,6 +348,7 @@
#define IOSF_BYTE_ENABLES_SHIFT 4
#define IOSF_BAR_SHIFT 1
#define IOSF_SB_BUSY (1<<0)
+#define IOSF_PORT_BUNIT 0x3
#define IOSF_PORT_PUNIT 0x4
#define IOSF_PORT_NC 0x11
#define IOSF_PORT_DPIO 0x12
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 9944d81..d43e457 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -90,6 +90,22 @@ void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
mutex_unlock(&dev_priv->dpio_lock);
}
+u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
+{
+ u32 val = 0;
+
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
+ PUNIT_OPCODE_REG_READ, reg, &val);
+
+ return val;
+}
+
+void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+{
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
+ PUNIT_OPCODE_REG_WRITE, reg, &val);
+}
+
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
{
u32 val = 0;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/3] drm/i915: move VLV DDR freq fetch into init_clock_gating
2013-10-28 18:14 [PATCH 1/3] drm/i915: add bunit read/write routines Jesse Barnes
@ 2013-10-28 18:14 ` Jesse Barnes
2013-10-28 18:14 ` [PATCH 3/3] drm/i915/vlv: update czclk freq if needed for high bandwidth modes Jesse Barnes
1 sibling, 0 replies; 5+ messages in thread
From: Jesse Barnes @ 2013-10-28 18:14 UTC (permalink / raw)
To: intel-gfx
We don't want it delayed with the RPS work.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_pm.c | 31 ++++++++++++++++++-------------
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bf5261f..d355b1a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4054,19 +4054,6 @@ static void valleyview_enable_rps(struct drm_device *dev)
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- switch ((val >> 6) & 3) {
- case 0:
- case 1:
- dev_priv->mem_freq = 800;
- break;
- case 2:
- dev_priv->mem_freq = 1066;
- break;
- case 3:
- dev_priv->mem_freq = 1333;
- break;
- }
- DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
@@ -5313,6 +5300,24 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
static void valleyview_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 val;
+
+ mutex_lock(&dev_priv->rps.hw_lock);
+ val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ mutex_unlock(&dev_priv->rps.hw_lock);
+ switch ((val >> 6) & 3) {
+ case 0:
+ case 1:
+ dev_priv->mem_freq = 800;
+ break;
+ case 2:
+ dev_priv->mem_freq = 1066;
+ break;
+ case 3:
+ dev_priv->mem_freq = 1333;
+ break;
+ }
+ DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 3/3] drm/i915/vlv: update czclk freq if needed for high bandwidth modes
2013-10-28 18:14 [PATCH 1/3] drm/i915: add bunit read/write routines Jesse Barnes
2013-10-28 18:14 ` [PATCH 2/3] drm/i915: move VLV DDR freq fetch into init_clock_gating Jesse Barnes
@ 2013-10-28 18:14 ` Jesse Barnes
1 sibling, 0 replies; 5+ messages in thread
From: Jesse Barnes @ 2013-10-28 18:14 UTC (permalink / raw)
To: intel-gfx
Needed to support large panel resolutions.
Tested-by: Josh Triplett <josh@joshtriplett.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_display.c | 64 ++++++++++++++++++++++++++++++++++++
2 files changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6a6eb8b..89109c4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1447,6 +1447,8 @@
#define CZCLK_FREQ_MASK 0xf
#define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
+#define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
+
/*
* Palette regs
*/
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 152d6a8..1bf811a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3851,6 +3851,67 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
I915_WRITE(BCLRPAT(crtc->pipe), 0);
}
+static void valleyview_adjust_czclk(struct drm_device *dev, bool up)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 val, divider;
+
+ switch (dev_priv->mem_freq) {
+ default:
+ case 800:
+ if (up)
+ divider = 3;
+ else
+ divider = 4;
+ break;
+ case 1066:
+ if (up)
+ divider = 7;
+ else
+ divider = 9;
+ break;
+ case 1333:
+ if (up)
+ divider = 9;
+ else
+ divider = 11;
+ break;
+ }
+
+ /* adjust czclk ratio */
+ mutex_lock(&dev_priv->dpio_lock);
+ val = vlv_cck_read(dev_priv, 0x6b);
+ val &= ~0xf;
+ val |= divider;
+ vlv_cck_write(dev_priv, 0x6b, val);
+
+ /* adjust self-refresh exit latency value */
+ val = vlv_bunit_read(dev_priv, 0x11);
+ val &= ~0x7f;
+ if (up)
+ val |= 0x12;
+ else
+ val |= 0xc;
+ vlv_bunit_write(dev_priv, 0x11, val);
+ mutex_unlock(&dev_priv->dpio_lock);
+}
+
+static void valleyview_modeset_global_resources(struct drm_device *dev)
+{
+ struct intel_crtc *crtc;
+ bool need_czclk_increase = false;
+
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
+ if (!crtc->base.enabled)
+ continue;
+
+ if (crtc->config.adjusted_mode.clock >= 3600)
+ need_czclk_increase = true;
+ }
+
+ valleyview_adjust_czclk(dev, need_czclk_increase);
+}
+
static void valleyview_crtc_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -10218,6 +10279,9 @@ static void intel_init_display(struct drm_device *dev)
}
} else if (IS_G4X(dev)) {
dev_priv->display.write_eld = g4x_write_eld;
+ } else if (IS_VALLEYVIEW(dev)) {
+ dev_priv->display.modeset_global_resources =
+ valleyview_modeset_global_resources;
}
/* Default just returns -ENODEV to indicate unsupported */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 1/3] drm/i915: add bunit read/write routines
@ 2013-10-28 20:46 Jesse Barnes
2013-10-28 20:46 ` [PATCH 3/3] drm/i915/vlv: update czclk freq if needed for high bandwidth modes Jesse Barnes
0 siblings, 1 reply; 5+ messages in thread
From: Jesse Barnes @ 2013-10-28 20:46 UTC (permalink / raw)
To: intel-gfx
For modifying self-refresh exit latency.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 16 ++++++++++++++++
3 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 20c409c..4cf7f60 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2356,6 +2356,8 @@ u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
+u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
+void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c6cc8e..6a6eb8b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -348,6 +348,7 @@
#define IOSF_BYTE_ENABLES_SHIFT 4
#define IOSF_BAR_SHIFT 1
#define IOSF_SB_BUSY (1<<0)
+#define IOSF_PORT_BUNIT 0x3
#define IOSF_PORT_PUNIT 0x4
#define IOSF_PORT_NC 0x11
#define IOSF_PORT_DPIO 0x12
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 9944d81..d43e457 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -90,6 +90,22 @@ void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
mutex_unlock(&dev_priv->dpio_lock);
}
+u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
+{
+ u32 val = 0;
+
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
+ PUNIT_OPCODE_REG_READ, reg, &val);
+
+ return val;
+}
+
+void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+{
+ vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
+ PUNIT_OPCODE_REG_WRITE, reg, &val);
+}
+
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
{
u32 val = 0;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 3/3] drm/i915/vlv: update czclk freq if needed for high bandwidth modes
2013-10-28 20:46 [PATCH 1/3] drm/i915: add bunit read/write routines Jesse Barnes
@ 2013-10-28 20:46 ` Jesse Barnes
2013-10-29 7:37 ` Daniel Vetter
0 siblings, 1 reply; 5+ messages in thread
From: Jesse Barnes @ 2013-10-28 20:46 UTC (permalink / raw)
To: intel-gfx
Needed to support large panel resolutions.
Tested-by: Josh Triplett <josh@joshtriplett.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_display.c | 64 ++++++++++++++++++++++++++++++++++++
2 files changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6a6eb8b..89109c4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1447,6 +1447,8 @@
#define CZCLK_FREQ_MASK 0xf
#define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
+#define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
+
/*
* Palette regs
*/
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 152d6a8..1bf811a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3851,6 +3851,67 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
I915_WRITE(BCLRPAT(crtc->pipe), 0);
}
+static void valleyview_adjust_czclk(struct drm_device *dev, bool up)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 val, divider;
+
+ switch (dev_priv->mem_freq) {
+ default:
+ case 800:
+ if (up)
+ divider = 3;
+ else
+ divider = 4;
+ break;
+ case 1066:
+ if (up)
+ divider = 7;
+ else
+ divider = 9;
+ break;
+ case 1333:
+ if (up)
+ divider = 9;
+ else
+ divider = 11;
+ break;
+ }
+
+ /* adjust czclk ratio */
+ mutex_lock(&dev_priv->dpio_lock);
+ val = vlv_cck_read(dev_priv, 0x6b);
+ val &= ~0xf;
+ val |= divider;
+ vlv_cck_write(dev_priv, 0x6b, val);
+
+ /* adjust self-refresh exit latency value */
+ val = vlv_bunit_read(dev_priv, 0x11);
+ val &= ~0x7f;
+ if (up)
+ val |= 0x12;
+ else
+ val |= 0xc;
+ vlv_bunit_write(dev_priv, 0x11, val);
+ mutex_unlock(&dev_priv->dpio_lock);
+}
+
+static void valleyview_modeset_global_resources(struct drm_device *dev)
+{
+ struct intel_crtc *crtc;
+ bool need_czclk_increase = false;
+
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
+ if (!crtc->base.enabled)
+ continue;
+
+ if (crtc->config.adjusted_mode.clock >= 3600)
+ need_czclk_increase = true;
+ }
+
+ valleyview_adjust_czclk(dev, need_czclk_increase);
+}
+
static void valleyview_crtc_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -10218,6 +10279,9 @@ static void intel_init_display(struct drm_device *dev)
}
} else if (IS_G4X(dev)) {
dev_priv->display.write_eld = g4x_write_eld;
+ } else if (IS_VALLEYVIEW(dev)) {
+ dev_priv->display.modeset_global_resources =
+ valleyview_modeset_global_resources;
}
/* Default just returns -ENODEV to indicate unsupported */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 3/3] drm/i915/vlv: update czclk freq if needed for high bandwidth modes
2013-10-28 20:46 ` [PATCH 3/3] drm/i915/vlv: update czclk freq if needed for high bandwidth modes Jesse Barnes
@ 2013-10-29 7:37 ` Daniel Vetter
0 siblings, 0 replies; 5+ messages in thread
From: Daniel Vetter @ 2013-10-29 7:37 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Mon, Oct 28, 2013 at 01:46:39PM -0700, Jesse Barnes wrote:
> Needed to support large panel resolutions.
>
> Tested-by: Josh Triplett <josh@joshtriplett.org>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_display.c | 64 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 66 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6a6eb8b..89109c4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1447,6 +1447,8 @@
> #define CZCLK_FREQ_MASK 0xf
> #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
>
> +#define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
> +
> /*
> * Palette regs
> */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 152d6a8..1bf811a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3851,6 +3851,67 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
> I915_WRITE(BCLRPAT(crtc->pipe), 0);
> }
>
> +static void valleyview_adjust_czclk(struct drm_device *dev, bool up)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 val, divider;
> +
> + switch (dev_priv->mem_freq) {
> + default:
> + case 800:
> + if (up)
> + divider = 3;
> + else
> + divider = 4;
> + break;
> + case 1066:
> + if (up)
> + divider = 7;
> + else
> + divider = 9;
> + break;
> + case 1333:
> + if (up)
> + divider = 9;
> + else
> + divider = 11;
> + break;
> + }
> +
> + /* adjust czclk ratio */
> + mutex_lock(&dev_priv->dpio_lock);
> + val = vlv_cck_read(dev_priv, 0x6b);
> + val &= ~0xf;
> + val |= divider;
> + vlv_cck_write(dev_priv, 0x6b, val);
> +
> + /* adjust self-refresh exit latency value */
> + val = vlv_bunit_read(dev_priv, 0x11);
> + val &= ~0x7f;
> + if (up)
> + val |= 0x12;
> + else
> + val |= 0xc;
> + vlv_bunit_write(dev_priv, 0x11, val);
> + mutex_unlock(&dev_priv->dpio_lock);
> +}
> +
> +static void valleyview_modeset_global_resources(struct drm_device *dev)
> +{
> + struct intel_crtc *crtc;
> + bool need_czclk_increase = false;
> +
> + list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
> + if (!crtc->base.enabled)
> + continue;
> +
> + if (crtc->config.adjusted_mode.clock >= 3600)
All our clocks are in kHz, so this is _really_ slow. To make debugging
this a bit easier I think we need a DRM_DEBUG_KMS line here that tells us
why we need the higher clock, e.g.
DRM_DEBUG_KMS("Increasing czclk due to pipe %s with dotclock %i\n",
pipe_name(crtc->pipe), crtc->config.adjusted_mode.clock);
Also, a quick comment either in the code or in the commit message that
explains quickly what this clock controls and why you've picked the right
one of the three clocks we have in the config would be good.
-Daniel
> + need_czclk_increase = true;
> + }
> +
> + valleyview_adjust_czclk(dev, need_czclk_increase);
> +}
> +
> static void valleyview_crtc_enable(struct drm_crtc *crtc)
> {
> struct drm_device *dev = crtc->dev;
> @@ -10218,6 +10279,9 @@ static void intel_init_display(struct drm_device *dev)
> }
> } else if (IS_G4X(dev)) {
> dev_priv->display.write_eld = g4x_write_eld;
> + } else if (IS_VALLEYVIEW(dev)) {
> + dev_priv->display.modeset_global_resources =
> + valleyview_modeset_global_resources;
> }
>
> /* Default just returns -ENODEV to indicate unsupported */
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2013-10-29 7:36 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2013-10-28 18:14 [PATCH 1/3] drm/i915: add bunit read/write routines Jesse Barnes
2013-10-28 18:14 ` [PATCH 2/3] drm/i915: move VLV DDR freq fetch into init_clock_gating Jesse Barnes
2013-10-28 18:14 ` [PATCH 3/3] drm/i915/vlv: update czclk freq if needed for high bandwidth modes Jesse Barnes
-- strict thread matches above, loose matches on Subject: below --
2013-10-28 20:46 [PATCH 1/3] drm/i915: add bunit read/write routines Jesse Barnes
2013-10-28 20:46 ` [PATCH 3/3] drm/i915/vlv: update czclk freq if needed for high bandwidth modes Jesse Barnes
2013-10-29 7:37 ` Daniel Vetter
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