From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 3/4] drm/i915: get a PC8 reference when enabling the power well Date: Thu, 31 Oct 2013 14:40:52 +0200 Message-ID: <1383223252.14628.12.camel@intelbox> References: <1383169226-16707-1-git-send-email-przanoni@gmail.com> <1383169226-16707-4-git-send-email-przanoni@gmail.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0801344142==" Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 282C4EFD07 for ; Thu, 31 Oct 2013 05:41:29 -0700 (PDT) In-Reply-To: <1383169226-16707-4-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org --===============0801344142== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-QFO7s8kHRR7WGzc4W5WC" --=-QFO7s8kHRR7WGzc4W5WC Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2013-10-30 at 19:40 -0200, Paulo Zanoni wrote: > From: Paulo Zanoni >=20 > In the current code, at haswell_modeset_global_resources, first we > decide if we want to enable/disable the power well, then we decide if > we want to enable/disable PC8. On the case where we're enabling PC8 > this works fine, but on the case where we disable PC8 due to a non-eDP > monitor being enabled, we first enable the power well and then disable > PC8. Although wrong, this doesn't seem to be causing any problems now, > and we don't even see anything in dmesg. But the patches for runtime > D3 turn this problem into a real bug, so we need to fix it. >=20 > This fixes the "modeset-non-lpsp" test from both "pc8" and > "runtime_pm" tests from intel-gpu-tools. >=20 > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_pm.c | 14 ++++++++++++-- > 1 file changed, 12 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index a0c907f..5b50083 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5547,6 +5547,8 @@ static void __intel_set_power_well(struct drm_devic= e *dev, bool enable) > bool is_enabled, enable_requested; > uint32_t tmp; > =20 > + WARN_ON(dev_priv->pc8.enabled); > + > tmp =3D I915_READ(HSW_PWR_WELL_DRIVER); > is_enabled =3D tmp & HSW_PWR_WELL_STATE_ENABLED; > enable_requested =3D tmp & HSW_PWR_WELL_ENABLE_REQUEST; > @@ -5591,16 +5593,24 @@ static void __intel_set_power_well(struct drm_dev= ice *dev, bool enable) > static void __intel_power_well_get(struct drm_device *dev, > struct i915_power_well *power_well) > { > - if (!power_well->count++) > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + > + if (!power_well->count++) { > + hsw_disable_package_c8(dev_priv); > __intel_set_power_well(dev, true); > + } > } > =20 > static void __intel_power_well_put(struct drm_device *dev, > struct i915_power_well *power_well) > { > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + > WARN_ON(!power_well->count); > - if (!--power_well->count) > + if (!--power_well->count) { > __intel_set_power_well(dev, false); > + hsw_enable_package_c8(dev_priv); > + } > } It would be better to add these __intel_set_power_well(), which has all the HSW specific bits already. --Imre > =20 > void intel_display_power_get(struct drm_device *dev, --=-QFO7s8kHRR7WGzc4W5WC Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQEcBAABAgAGBQJSck/UAAoJEORIIAnNuWDFosoIAINqnHafnHrA4lShwgznm4bW pGMMrWrn/8gcVMcQOkbeWuLBD/FPj6rgKDvG85lvvaSnDL5ogoZTYeDFYcTIjup1 0St7ouuOqR54j27V9dp7RNZycs/1jSKmQSJMCgkX0C++GBqglDzqW/0LGiNLNkiX pCZGDzmWdYjJmL8umYnj8IWkowZMdNtDf08SZC3+YeO5fZZZkQ9+xsj9U5m/qeA7 IU65ldGp1VFpbgGG9/z02BvE8oXpE+dmk+DVTg5wOQCSM1J+wfqR4h+QokzMYJrT 9Tv6EidzcJwAT9e3da/VsMnwZD9mzOmoFp0OvIOHNVeV0/xGznayvdQsBjWcHg0= =+Urk -----END PGP SIGNATURE----- --=-QFO7s8kHRR7WGzc4W5WC-- --===============0801344142== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0801344142==--