[PATCH 00/62] Broadwell kernel driver support

[Ben Widawsky <benjamin.widawsky@intel.com>]

It is my honor and privilege to submit basic Broadwell support on behalf
of Intel.

The patch series includes support for Broadwell which should bring it up
to feature parity with Haswell. As you'll note, the patches have
received some revisions and review already. This is due to our new
process (more on this below). We will be rolling out the new Broadwell
goodness over time.

Broadwell represents the next generation (GEN8) in Intel graphics
processing hardware. Broadwell graphics bring some of the biggest
changes we've seen on the execution and memory management side of the
GPU. (There are equally large and exciting changes for the userspace
drivers.)

My request to reviewers is: I haven't touched these much at all since
submitting to the internal mailing list. Most changes are due to rebase.
Try to keep bikesheds to a minimum. We want to try to get this code in
the 3.13 kernel, so we have a nice base to actually stabilize and
improve features for the 3.14 release. Remember, we have that handy
'preliminary hardware support' to allow people to opt-in to this early
enabling code. So I'm shooting for stable "end-userable" BDW code in
3.14.

Note that the last few workarounds likely won't be needed, but I think
we can include them until we know for sure otherwise.

Aside from the usual set of things we need to update when simply
enabling a new platform, What follows are some of the major changes from
HSW->BDW:

* There is no longer a forcewake write FIFO. *Most* writes must explicitly
wake the GPU.

* Interrupt registers have been completely reorganized.

* PTEs format and cachability settings have changed to more resemble x86
PTEs, and PAT
  * Address space increases, and as such many commands require changing

* Page table structures have changed for the Per Process GTT. The new
structure more resembles traditional page tables with registers defining
page directory base.

The latter two changes were the real challenge in enabling the platform
and getting things to actually work - though in hindsight, they seem so
trivial :-)

You may find these patches here:
http://cgit.freedesktop.org/~bwidawsk/drm-intel/log/?h=broadwell

I'll be posting patches for libdrm, and intel-gpu-tools in the next day
or two.  They are also ready to go, I just need to do a quick once over.
At this point, feel free to stop reading.




I wanted to talk a bit about some of the changes on the development side
which are enabling us to get code out way before silicon ships. Again,
I'd like to point out that the amount of changes on BDW dwarfs any other
silicon iteration during my tenure, and certainly can compete with the
likes of the gen3->gen4 changes.

Broadwell development for the i915 driver began last November, 2012.
With the help of some awesome people we managed to enable a simulation
environment for Linux graphics development. While this was not the first
time the OTC teams had used simulation for development, it did mark the
first time we were using it to simulate and run the entire software
stack and model most of the HW. The previous use of simulation really
didn't provide anything useful for the kernel driver, and faked enough
of the relevant user space interactions to cause some worry.

Another new process was the invention and usage of an internal mailing
list, where we could talk about, and review code that we did not yet
have permission to open source.

Sometime around mid December, we had code which could run glxgears. The
magic is really what happened after. For the last 10 months (give or
take), Daniel Vetter has been maintaining our internal repository for
development. Providing continuous rebases on the very fast based
upstream tree (and less rapid internal development). In addition, we've
gotten support from our QA team to test our code internally on the
simulator. We've even gotten other groups in Intel (outside of OTC) to
contribute to all parts of the stack.

For the foreseeable future, all future platforms will follow this same
enabling procedure that allows us to get better, more stable code, well
before silicon ships. The goal is to get stable drivers in the kernel
release that coincides with the time silicon ships.

As such, a quick thanks:
* Daniel Vetter, for the incredible job he did on maintaining our
internal repository.

* Chris Wilson, for getting me a mostly functional DDX within days of a
working kernel - for that oh so cool glxgears screenshot.

* Ken Graunke, for actually making mesa work with the absurd amount of
changes on the EUs. (and therefore, also enabling said screenshot).

* The Intel internal simulation team, for helping to provide us the
necessary tools to make it all happen.

* The Intel [Windows] graphics team, for providing support, and easing
the process for open source approval

Art Runyan (1):
  drm/i915/bdw: Add BDW DDI buffer translation values

Ben Widawsky (44):
  drm/i915/bdw: IS_GEN8 definition
  drm/i915/bdw: Handle forcewake for writes on gen8
  drm/i915/bdw: Add device IDs
  drm/i915/bdw: Fences on gen8 look just like gen7
  drm/i915/bdw: Swizzling support
  drm/i915/bdw: HW context support
  drm/i915/bdw: Clock gating init
  drm/i915/bdw: display stuff
  drm/i915/bdw: support GMS and GGMS changes
  drm/i915/bdw: Implement interrupt changes
  drm/i915/bdw: Add interrupt info to debugfs
  drm/i915/bdw: Support 64b relocations
  drm/i915/bdw: dispatch updates (64b related)
  drm/i915/bdw: Update MI_FLUSH_DW
  drm/i915/bdw: debugfs updates
  drm/i915/bdw: Update relevant error state
  drm/i915/bdw: Make gen8_gmch_probe
  drm/i915/bdw: Create gen8_gtt_pte_t
  drm/i915/bdw: Add GTT functions
  drm/i915/bdw: Support BDW caching
  drm/i915/bdw: Implement Full Force Miss disables
  drm/i915/bdw: PPGTT init & cleanup
  drm/i915/bdw: Initialize the PDEs
  drm/i915/bdw: Implement PPGTT clear range
  drm/i915/bdw: Implement PPGTT insert
  drm/i915/bdw: Implement PPGTT enable
  drm/i915/bdw: unleash PPGTT
  drm/i915/bdw: Render ring flushing
  drm/i915/bdw: BSD init for gen8 also
  drm/i915/bdw: ppgtt info in debugfs
  drm/i915/bdw: Implement WaSwitchSolVfFArbitrationPriority
  drm/i915/bdw: Use The GT mailbox for IPS enable/disable
  drm/i915/bdw: Support eDP PSR
  drm/i915/bdw: Use HSW formula for ring freq scaling
  drm/i915/bdw: Don't wait for c0 threads on forcewake
  drm/i915/bdw: Create a separate BDW rps enable
  drm/i915/bdw: Disable semaphores
  drm/i915/bdw: Implement edp PSR workarounds
  drm/i915/bdw: BWGTLB clock gate disable
  drm/i915/bdw: Disable centroid pixel perf optimization
  drm/i915/bdw: Sampler power bypass disable
  drm/i915/bdw: Limit SDE poly depth FIFO to 2
  drm/i915/bdw: conservative SBE VUE cache mode
  drm/i915/bdw: WaSingleSubspanDispatchOnAALinesAndPoints

Damien Lespiau (2):
  drm/i915/bdw: Broadwell has 3 pipes
  drm/i915/bdw: Broadwell has a max port clock of 300Mhz on HDMI

Daniel Vetter (1):
  drm/i915/bdw: Disable PPGTT for now

Paulo Zanoni (11):
  drm/i915/bdw: add IS_BROADWELL macro
  drm/i915/bdw: add Broadwell sprite/plane/cursor checks
  drm/i915/bdw: Broadwell also has the "power down well"
  drm/i915/bdw: pretend we have LPT LP on Broadwell
  drm/i915/bdw: get the correct LCPLL frequency on Broadwell
  drm/i915/bdw: on Broadwell, the panel fitter is on the pipe
  drm/i915/bdw: Broadwell has PIPEMISC
  drm/i915/bdw: add BDW DDI buf translations for eDP
  drm/i915/bdw: add support for BDW DP voltage swings and pre-emphasis
  drm/i915/bdw: BDW also has only 2 FDI lanes
  drm/i915/bdw: check DPD on port D when setting the DDI buffers

Ville Syrjälä (3):
  drm/i915/bdw: Don't muck with gtt_size on Gen8 when PPGTT setup fails
  drm/i915/bdw: Use pipe CSC on Broadwell
  drm/i915/bdw: Add Broadwell display FIFO limits

 arch/x86/kernel/early-quirks.c             |  12 +
 drivers/gpu/drm/i915/i915_debugfs.c        | 109 ++++++-
 drivers/gpu/drm/i915/i915_drv.c            |  34 +-
 drivers/gpu/drm/i915/i915_drv.h            |  36 ++-
 drivers/gpu/drm/i915/i915_gem.c            |   3 +
 drivers/gpu/drm/i915/i915_gem_context.c    |   3 +
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  35 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c        | 500 +++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_gpu_error.c      |   2 +
 drivers/gpu/drm/i915/i915_irq.c            | 327 +++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h            | 117 ++++++-
 drivers/gpu/drm/i915/intel_ddi.c           | 126 ++++++--
 drivers/gpu/drm/i915/intel_display.c       |  80 ++++-
 drivers/gpu/drm/i915/intel_dp.c            |  55 +++-
 drivers/gpu/drm/i915/intel_hdmi.c          |   2 +-
 drivers/gpu/drm/i915/intel_pm.c            | 168 +++++++++-
 drivers/gpu/drm/i915/intel_ringbuffer.c    | 187 ++++++++++-
 drivers/gpu/drm/i915/intel_sprite.c        |   5 +-
 drivers/gpu/drm/i915/intel_uncore.c        |  56 +++-
 include/drm/i915_drm.h                     |   4 +
 include/drm/i915_pciids.h                  |  27 ++
 21 files changed, 1771 insertions(+), 117 deletions(-)

-- 
1.8.4.2

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