From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 21/62] drm/i915/bdw: Support BDW caching Date: Tue, 05 Nov 2013 17:19:52 +0200 Message-ID: <1383664792.7273.8.camel@intelbox> References: <1383451680-11173-1-git-send-email-benjamin.widawsky@intel.com> <1383451680-11173-22-git-send-email-benjamin.widawsky@intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1821938359==" Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 38A17EFDEF for ; Tue, 5 Nov 2013 07:19:56 -0800 (PST) In-Reply-To: <1383451680-11173-22-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Ben Widawsky Cc: Daniel Vetter , Intel GFX , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org --===============1821938359== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-T2PgGbjn7cFCAvs0aC2a" --=-T2PgGbjn7cFCAvs0aC2a Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sat, 2013-11-02 at 21:07 -0700, Ben Widawsky wrote: > BDW caching works differently than the previous generations. Instead of > having bits in the PTE which directly control how the page is cached, > the 3 PTE bits PWT PCD and PAT provide an index into a PAT defined by > register 0x40e0. This style of caching is functionally equivalent to how > it works on HSW and before. >=20 > v2: Tiny bikeshed as discussed on internal irc. >=20 > v3: Squash in patch from Ville to mirror the x86 PAT setup more like > in arch/x86/mm/pat.c. Primarily, the 0th index will be WB, and not > uncached. >=20 > Signed-off-by: Ben Widawsky (v1) > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 42 +++++++++++++++++++++++++++++++= ++++++ > drivers/gpu/drm/i915/i915_reg.h | 1 + > 2 files changed, 43 insertions(+) >=20 > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i= 915_gem_gtt.c > index df992dc..02de12d 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -58,12 +58,21 @@ typedef uint64_t gen8_gtt_pte_t; > #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) > #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) > =20 > +#define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) > +#define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ > +#define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ > +#define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ > + > static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, > enum i915_cache_level level, > bool valid) > { > gen8_gtt_pte_t pte =3D valid ? _PAGE_PRESENT | _PAGE_RW : 0; > pte |=3D addr; > + if (level !=3D I915_CACHE_NONE) > + pte |=3D PPAT_CACHED_INDEX; > + else > + pte |=3D PPAT_UNCACHED_INDEX; > return pte; > } > =20 > @@ -805,6 +814,7 @@ static void i915_gtt_color_adjust(struct drm_mm_node = *node, > *end -=3D 4096; > } > } > + > void i915_gem_setup_global_gtt(struct drm_device *dev, > unsigned long start, > unsigned long mappable_end, > @@ -1002,6 +1012,36 @@ static int ggtt_probe_common(struct drm_device *de= v, > return ret; > } > =20 > +/* The GGTT and PPGTT need a private PPAT setup in order to handle cache= ability > + * bits. When using advanced contexts each context stores its own PAT, b= ut > + * writing this data shouldn't be harmful even in those cases. */ > +static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv) > +{ > +#define GEN8_PPAT_UC (0<<0) > +#define GEN8_PPAT_WC (1<<0) > +#define GEN8_PPAT_WT (2<<0) > +#define GEN8_PPAT_WB (3<<0) > +#define GEN8_PPAT_ELLC_OVERRIDE (0<<2) > +#define GEN8_PPAT_LLC (1<<2) > +#define GEN8_PPAT_LLCELLC (2<<2) > +#define GEN8_PPAT_LLCeLLC (3<<2) /* BSPEC mistake? */ The LLC, LLCELLC encodings don't match the bspec either. If the above are the correct values it would be nice to have a comment after those too. Otherwise looks ok: Reviewed-by: Imre Deak > +#define GEN8_PPAT_AGE(x) (x<<4) > +#define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) > + uint64_t pat; > + > + pat =3D GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal = objects, no eLLC */ > + GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something= pointing to ptes? */ > + GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout w= ith eLLC */ > + GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached obje= cts, mostly for scanout */ > + GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0))= | > + GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1))= | > + GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2))= | > + GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3))= ; > + > + I915_WRITE(GEN8_PRIVATE_PAT, pat); > + I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); > +} > + > static int gen8_gmch_probe(struct drm_device *dev, > size_t *gtt_total, > size_t *stolen, > @@ -1027,6 +1067,8 @@ static int gen8_gmch_probe(struct drm_device *dev, > gtt_size =3D gen8_get_total_gtt_size(snb_gmch_ctl); > *gtt_total =3D (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; > =20 > + gen8_setup_private_ppat(dev_priv); > + > ret =3D ggtt_probe_common(dev, gtt_size); > =20 > dev_priv->gtt.base.clear_range =3D gen8_ggtt_clear_range; > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index b801b88..9929750 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -664,6 +664,7 @@ > #define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3) > #define RING_FAULT_VALID (1<<0) > #define DONE_REG 0x40b0 > +#define GEN8_PRIVATE_PAT 0x40e0 > #define BSD_HWS_PGA_GEN7 (0x04180) > #define BLT_HWS_PGA_GEN7 (0x04280) > #define VEBOX_HWS_PGA_GEN7 (0x04380) --=-T2PgGbjn7cFCAvs0aC2a Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQEcBAABAgAGBQJSeQyYAAoJEORIIAnNuWDFRUEIAOwtWG5BaBNmw13eCOIbM/O5 B31appVNOexJa1Y7iobxYI80+I5vwe74qQ0JkQoB0OzxS9LOK7nJVHHNxkzt9MLk vMSYScrTHU4rh99iQVw0kLDLeVwEoR5wrIfniQew8mRnvvI5ADYaP6jOMysOekIw sNAginCM/yfM4BXF8bN97Ll8FV4QmE1U7YtqHr7BjKLt2vPVxoRexqBIb2wQ3p8U sLt0sOu3jfwSmB1PizeXD05xZyBLpEAKPpethEowApoLrDZF5G3WRbQraFoD9/rL dUo1wLr3yY8SVWQATDwlOmozpaHM6SuWydrcc23z7WAdzFYnI9b4Q6h/ZYEX9KA= =MVIL -----END PGP SIGNATURE----- --=-T2PgGbjn7cFCAvs0aC2a-- --===============1821938359== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1821938359==--