From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: [PATCH 4/5] intel/bdw/aub: Update AUB trace block writes for 48-bit addressing. Date: Wed, 6 Nov 2013 09:15:31 -0800 Message-ID: <1383758132-28273-5-git-send-email-benjamin.widawsky@intel.com> References: <1383758132-28273-1-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1383758132-28273-1-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org To: DRI Devel , Intel GFX Cc: Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org From: Kenneth Graunke Since our aub file dumping's GTT handling is totally fake, we always put everything in the low 4GB anyway and shouldn't ever need to set AddressHigh to anything other than 0. Signed-off-by: Kenneth Graunke [ben: slight commit message change] Signed-off-by: Ben Widawsky --- intel/intel_bufmgr_gem.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 32a226c..3eb6e2e 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -1944,12 +1944,14 @@ aub_write_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype, aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | - (5 - 2)); + ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2)); aub_out(bufmgr_gem, AUB_TRACE_MEMTYPE_GTT | type | AUB_TRACE_OP_DATA_WRITE); aub_out(bufmgr_gem, subtype); aub_out(bufmgr_gem, bo_gem->aub_offset + offset); aub_out(bufmgr_gem, size); + if (bufmgr_gem->gen >= 8) + aub_out(bufmgr_gem, 0); aub_write_bo_data(bo, offset, size); } @@ -2034,12 +2036,14 @@ aub_build_dump_ringbuffer(drm_intel_bufmgr_gem *bufmgr_gem, */ aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | - (5 - 2)); + ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2)); aub_out(bufmgr_gem, AUB_TRACE_MEMTYPE_GTT | ring | AUB_TRACE_OP_COMMAND_WRITE); aub_out(bufmgr_gem, 0); /* general/surface subtype */ aub_out(bufmgr_gem, bufmgr_gem->aub_offset); aub_out(bufmgr_gem, ring_count * 4); + if (bufmgr_gem->gen >= 8) + aub_out(bufmgr_gem, 0); /* FIXME: Need some flush operations here? */ aub_out_data(bufmgr_gem, ringbuffer, ring_count * 4); @@ -2952,11 +2956,13 @@ drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable) aub_out(bufmgr_gem, 0); /* comment len */ /* Set up the GTT. The max we can handle is 256M */ - aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | (5 - 2)); + aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | ((bufmgr_gem->gen >= 8 ? 6 : 5) - 2)); aub_out(bufmgr_gem, AUB_TRACE_MEMTYPE_NONLOCAL | 0 | AUB_TRACE_OP_DATA_WRITE); aub_out(bufmgr_gem, 0); /* subtype */ aub_out(bufmgr_gem, 0); /* offset */ aub_out(bufmgr_gem, gtt_size); /* size */ + if (bufmgr_gem->gen >= 8) + aub_out(bufmgr_gem, 0); for (i = 0x000; i < gtt_size; i += 4, entry += 0x1000) { aub_out(bufmgr_gem, entry); } -- 1.8.4.2