From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: [PATCH 12/21] drm/i915/bdw: posting read the full 64b PTE Date: Thu, 7 Nov 2013 21:40:42 -0800 Message-ID: <1383889251-498-12-git-send-email-benjamin.widawsky@intel.com> References: <1383889251-498-1-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 7BEC7EDFA1 for ; Thu, 7 Nov 2013 22:11:45 -0800 (PST) In-Reply-To: <1383889251-498-1-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Intel GFX Cc: Ben Widawsky , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org For our posting read we were reading only 32b on BDW. There was a FIXME already - the warning is annoying. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 638fd09..3620a1b 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -899,12 +899,9 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, * registers and PTEs are within the same BAR that they are potentially * of NUMA access patterns. Therefore, even with the way we assume * hardware should work, we must keep this posting read for paranoia. - * - * FIXME(BDW): The check is bogus - we read 32bit but the ptes are - * 64bit. */ if (i != 0) - WARN_ON(readl(>t_entries[i-1]) + WARN_ON(readq(>t_entries[i-1]) != gen8_pte_encode(addr, level, true)); #if 0 /* TODO: Still needed on GEN8? */ -- 1.8.4.2