From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 05/13] drm/i915: fix gen2-gen3 backlight set Date: Wed, 13 Nov 2013 11:12:01 +0200 Message-ID: <1384333921.25182.2.camel@intelbox> References: <5da7c92cb5634c7b7349065fe82f46c0564a6715.1383920621.git.jani.nikula@intel.com> <1384293603.2462.39.camel@ideak-mobl> <87habgso3p.fsf@intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0959839120==" Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id C306DF9C3E for ; Wed, 13 Nov 2013 01:12:05 -0800 (PST) In-Reply-To: <87habgso3p.fsf@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0959839120== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-+sTkepbuAtb14zJE/9Dh" --=-+sTkepbuAtb14zJE/9Dh Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2013-11-13 at 10:27 +0200, Jani Nikula wrote: > On Wed, 13 Nov 2013, Imre Deak wrote: > > On Fri, 2013-11-08 at 16:48 +0200, Jani Nikula wrote: > >> Signed-off-by: Jani Nikula > >> --- > >> drivers/gpu/drm/i915/intel_panel.c | 10 +++++++--- > >> 1 file changed, 7 insertions(+), 3 deletions(-) > >>=20 > >> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915= /intel_panel.c > >> index a821949..e82b2dd 100644 > >> --- a/drivers/gpu/drm/i915/intel_panel.c > >> +++ b/drivers/gpu/drm/i915/intel_panel.c > >> @@ -555,7 +555,7 @@ static void i9xx_set_backlight(struct intel_connec= tor *connector, u32 level) > >> { > >> struct drm_device *dev =3D connector->base.dev; > >> struct drm_i915_private *dev_priv =3D dev->dev_private; > >> - u32 tmp; > >> + u32 tmp, mask; > >> =20 > >> if (is_backlight_combination_mode(dev)) { > >> u32 max =3D intel_panel_get_max_backlight(connector); > >> @@ -570,10 +570,14 @@ static void i9xx_set_backlight(struct intel_conn= ector *connector, u32 level) > >> pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc); > >> } > >> =20 > >> - if (INTEL_INFO(dev)->gen < 4) > >> + if (IS_GEN4(dev)) { > >> + mask =3D BACKLIGHT_DUTY_CYCLE_MASK; > >> + } else { > >> level <<=3D 1; > >> + mask =3D BACKLIGHT_DUTY_CYCLE_MASK_PNV; > >> + } > > > > According to the gen2/3 bspec I have, the correct mask is > > BACKLIGHT_DUTY_CYCLE_MASK_PNV only in case of IS_PINEVIEW(dev), for > > everything else it's BACKLIGHT_DUTY_CYCLE_MASK. >=20 > What you say is correct, but we've treated all gen2/3 similar to PNV > since >=20 > commit ca88479c1c3b7b1a9f94320745f5331e1de77f80 > Author: Keith Packard > Date: Fri Nov 18 11:09:24 2011 -0800 >=20 > drm/i915: Treat pre-gen4 backlight duty cycle value consistently >=20 > i.e. we only use the high 15 bits for all gen2/3. For non-PNV this just > means the lowest bit is always zero. For PNV the lowest bit has a > different meaning in both the PWM freq and duty cycle fields. >=20 > I don't want to take any chances by changing this behaviour. I realize > there's zero comments about this in the code; would you like me to add > some? Yea, looking at the log would've been useful.. I see now from that commit that there was a problem with setting bit 0 on some old HW, so I'm ok to leave this as-is. A comment would be nice, but either way: Reviewed-by: Imre Deak --=-+sTkepbuAtb14zJE/9Dh Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQEcBAABAgAGBQJSg0JhAAoJEORIIAnNuWDFPCQIALUNrbyEsdfz0i32/+zottl1 +IhN+RFERPaCnqNy7Ccz/yXsqLZdoXq+HgEBkWjkYqRZFU9vfF6dMYK6WUVj4VmF vgVG9qapM9zJrLtabaZvKh/BaqJH8TUgDe/yQL4fKBbIaWDI7PhA0bYr42QcnG+8 3Rpw06lXaJTi6h05E5f8K9jsUF5veLnM4mcd61sv5drRJ5WuqjSrSzo5tALoJXtI F1CP5HguVa3jDjvbvzoCK2Ev1bcEyoGW/Kef0cLO279UtcqESzd2sYETIVKoTOKz THmBwGK8d6T8oCA5bcfIzxwcFgTI+04Po6pw/RG0tSph8q1536eBEf0gOo29NeE= =fXv1 -----END PGP SIGNATURE----- --=-+sTkepbuAtb14zJE/9Dh-- --===============0959839120== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0959839120==--