From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: [PATCH 01/12] drm/i915: Fix BDW PPGTT error path Date: Mon, 25 Nov 2013 09:54:32 -0800 Message-ID: <1385402083-8719-2-git-send-email-benjamin.widawsky@intel.com> References: <1385402083-8719-1-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail.bwidawsk.net (bwidawsk.net [166.78.191.112]) by gabe.freedesktop.org (Postfix) with ESMTP id C74C0FAE10 for ; Mon, 25 Nov 2013 09:54:49 -0800 (PST) In-Reply-To: <1385402083-8719-1-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Intel GFX Cc: Ben Widawsky , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org When we fail for some reason on loading the PDPs, it would be wise to disable the PPGTT in the ring registers. If we do not do this, we have undefined results. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gtt.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index efb5dab..1a5272c 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -238,10 +238,16 @@ static int gen8_ppgtt_enable(struct drm_device *dev) for_each_ring(ring, dev_priv, j) { ret = gen8_write_pdp(ring, i, addr); if (ret) - return ret; + goto err_out; } } return 0; + +err_out: + for_each_ring(ring, dev_priv, j) + I915_WRITE(RING_MODE_GEN7(ring), + _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE)); + return ret; } static void gen8_ppgtt_clear_range(struct i915_address_space *vm, -- 1.8.4.2