Re: [PATCH 3/4] drm/i915: Disable/Enable PM Intrrupts based on the current freq.

Daniel Vetter
2013-12-09T08:11:27Z

On Sun, Dec 08, 2013 at 02:16:45PM +0530, deepak.s@intel.com wrote:
> From: Deepak S <deepak.s@intel.com>
>
> When current delay is already at max delay, Let's disable the PM UP
> THRESHOLD INTRRUPTS, so that we will not get further interrupts until
> current delay is less than max delay, Also request for the PM DOWN
> THRESHOLD INTRRUPTS to indicate the decrease in clock freq. and
> viceversa for PM DOWN THRESHOLD INTRRUPTS.
>
> Signed-off-by: Deepak S <deepak.s@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 +++
> drivers/gpu/drm/i915/i915_irq.c | 31 +++++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/intel_pm.c | 3 +++
> 3 files changed, 35 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a62ac0c..d52a2db 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -915,6 +915,9 @@ struct intel_gen6_power_mgmt {
> u8 rp0_delay;
> u8 hw_max;
>
> + u8 rp_up_masked;
> + u8 rp_down_masked;

Just a quick bikeshed: Real bool variables with symbolic false/true
preferred. But maybe hold off with resending until someone does a real
review ;-)
-Daniel

> +
> int last_adj;
> enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 4bde03a..cd82fdd 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -996,7 +996,20 @@ static void gen6_pm_rps_work(struct work_struct *work)
> adj *= 2;
> else
> adj = 1;
> - new_delay = dev_priv->rps.cur_delay + adj;
> +
> + if (dev_priv->rps.cur_delay >= dev_priv->rps.max_delay) {
> + I915_WRITE(GEN6_PMINTRMSK,
> + I915_READ(GEN6_PMINTRMSK) | 1 << 5);
> + dev_priv->rps.rp_up_masked = 1;
> + new_delay = dev_priv->rps.cur_delay;
> + } else
> + new_delay = dev_priv->rps.cur_delay + adj;
> +
> + if (dev_priv->rps.rp_down_masked) {
> + I915_WRITE(GEN6_PMINTRMSK,
> + I915_READ(GEN6_PMINTRMSK) | ~(1 << 4));
> + dev_priv->rps.rp_down_masked = 0;
> + }
>
> /*
> * For better performance, jump directly
> @@ -1015,7 +1028,21 @@ static void gen6_pm_rps_work(struct work_struct *work)
> adj *= 2;
> else
> adj = -1;
> - new_delay = dev_priv->rps.cur_delay + adj;
> +
> + if (dev_priv->rps.cur_delay <= dev_priv->rps.max_delay) {
> + I915_WRITE(GEN6_PMINTRMSK,
> + I915_READ(GEN6_PMINTRMSK) | 1 << 4);
> + dev_priv->rps.rp_down_masked = 1;
> + new_delay = dev_priv->rps.cur_delay;
> + } else
> + new_delay = dev_priv->rps.cur_delay + adj;
> +
> + if (dev_priv->rps.rp_up_masked) {
> + I915_WRITE(GEN6_PMINTRMSK,
> + I915_READ(GEN6_PMINTRMSK) | ~(1 << 5));
> + dev_priv->rps.rp_up_masked = 0;
> + }
> +
> } else { /* unknown event */
> new_delay = dev_priv->rps.cur_delay;
> }
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 716ca24..6b80ec4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4186,6 +4186,9 @@ static void valleyview_enable_rps(struct drm_device *dev)
> vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
> dev_priv->rps.rpe_delay);
>
> + dev_priv->rps.rp_up_masked = 0;
> + dev_priv->rps.rp_down_masked = 0;
> +
> valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
>
> gen6_enable_rps_interrupts(dev);
> --
> 1.8.4.2
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch