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From: Imre Deak <imre.deak@intel.com>
To: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/5] drm/i915: vlv: W/a for hotplug/manual VGA detection
Date: Tue, 17 Dec 2013 22:32:42 +0200	[thread overview]
Message-ID: <1387312362.3596.1.camel@ideak-mobl> (raw)
In-Reply-To: <1387060712-5081-5-git-send-email-rodrigo.vivi@gmail.com>

On Sat, 2013-12-14 at 20:38 -0200, Rodrigo Vivi wrote:
> From: Imre Deak <imre.deak@intel.com>
> 
> At least on my VLV stepping VGA detection doesn't work in certain cases.
> One such case is when all pipes are off and VGA is plugged in. Another
> case reported by Joonas Lahtinen (also on the same stepping) is booting
> with VGA disconnected where we incorrectly report that VGA is connected.
> At least in the first case writing the FORCE bit in the ADPA reg will
> get stuck, i.e. the detection never completes.
> 
> Both cases seem to be solved by disabling DPIO clock gating based on the
> PSR state. As I haven't found any trace that this would be a known
> issue, I can only speculate that both the DPIO HW block and the HW
> block responsible for VGA detection uses the same clock source which gets
> gated even though PSR is inactive.
> 
> I haven't measured if and how this change affects our power savings.
> 
> Reported-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

Please ignore this, I'll send a v2.

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 5 +++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f1eece4..726c3ce 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1451,6 +1451,9 @@
>  # define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
>  # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
>  
> +#define DPPSR_CGDIS_VLV                (dev_priv->info->display_mmio_offset + 0x6204)
> +# define DPIOUNIT_PSR_CLOCK_GATING_DISABLE     (1 << 6)
> +
>  #define RENCLK_GATE_D2		0x6208
>  #define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
>  #define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 465304a..4208065 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5438,6 +5438,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  
>  	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
>  
> +	/* Wa to make VGA hotplug and manual detection work. */
> +	val = I915_READ(DPPSR_CGDIS_VLV);
> +	val |= DPIOUNIT_PSR_CLOCK_GATING_DISABLE;
> +	I915_WRITE(DPIOUNIT_PSR_CLOCK_GATING_DISABLE, val);
> +
>  	/* WaDisableEarlyCull:vlv */
>  	I915_WRITE(_3D_CHICKEN3,
>  		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));

  reply	other threads:[~2013-12-17 20:33 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-14 22:38 [PATCH 0/5] drm-intel-collector - update Rodrigo Vivi
2013-12-14 22:38 ` [PATCH 1/5] drm/i915: Asynchronously perform the set-base for a simple modeset Rodrigo Vivi
2013-12-14 22:38 ` [PATCH 2/5] drm/i915: parse backlight modulation frequency from the BIOS VBT Rodrigo Vivi
2013-12-16  9:04   ` Daniel Vetter
2013-12-14 22:38 ` [PATCH 3/5] drm/i915: i830M has watermarks like i855 Rodrigo Vivi
2014-01-10 11:09   ` Ville Syrjälä
2013-12-14 22:38 ` [PATCH 4/5] drm/i915: vlv: W/a for hotplug/manual VGA detection Rodrigo Vivi
2013-12-17 20:32   ` Imre Deak [this message]
2013-12-14 22:38 ` [PATCH 5/5] drm/i915: Only use read-back pipe config Rodrigo Vivi

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