From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 4/5] drm/i915: vlv: W/a for hotplug/manual VGA detection Date: Tue, 17 Dec 2013 22:32:42 +0200 Message-ID: <1387312362.3596.1.camel@ideak-mobl> References: <1387060712-5081-1-git-send-email-rodrigo.vivi@gmail.com> <1387060712-5081-5-git-send-email-rodrigo.vivi@gmail.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 7F32D106A81 for ; Tue, 17 Dec 2013 12:33:17 -0800 (PST) In-Reply-To: <1387060712-5081-5-git-send-email-rodrigo.vivi@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Sat, 2013-12-14 at 20:38 -0200, Rodrigo Vivi wrote: > From: Imre Deak > > At least on my VLV stepping VGA detection doesn't work in certain cases. > One such case is when all pipes are off and VGA is plugged in. Another > case reported by Joonas Lahtinen (also on the same stepping) is booting > with VGA disconnected where we incorrectly report that VGA is connected. > At least in the first case writing the FORCE bit in the ADPA reg will > get stuck, i.e. the detection never completes. > > Both cases seem to be solved by disabling DPIO clock gating based on the > PSR state. As I haven't found any trace that this would be a known > issue, I can only speculate that both the DPIO HW block and the HW > block responsible for VGA detection uses the same clock source which gets > gated even though PSR is inactive. > > I haven't measured if and how this change affects our power savings. > > Reported-by: Joonas Lahtinen > Signed-off-by: Imre Deak > Signed-off-by: Rodrigo Vivi Please ignore this, I'll send a v2. > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_pm.c | 5 +++++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index f1eece4..726c3ce 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1451,6 +1451,9 @@ > # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) > # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) > > +#define DPPSR_CGDIS_VLV (dev_priv->info->display_mmio_offset + 0x6204) > +# define DPIOUNIT_PSR_CLOCK_GATING_DISABLE (1 << 6) > + > #define RENCLK_GATE_D2 0x6208 > #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) > #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 465304a..4208065 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5438,6 +5438,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > > I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); > > + /* Wa to make VGA hotplug and manual detection work. */ > + val = I915_READ(DPPSR_CGDIS_VLV); > + val |= DPIOUNIT_PSR_CLOCK_GATING_DISABLE; > + I915_WRITE(DPIOUNIT_PSR_CLOCK_GATING_DISABLE, val); > + > /* WaDisableEarlyCull:vlv */ > I915_WRITE(_3D_CHICKEN3, > _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));