From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 2/2] drm/i915: fix wrong PLL debug messages. Date: Wed, 8 Jan 2014 11:12:28 -0200 Message-ID: <1389186748-1954-2-git-send-email-przanoni@gmail.com> References: <1389186748-1954-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-qe0-f46.google.com (mail-qe0-f46.google.com [209.85.128.46]) by gabe.freedesktop.org (Postfix) with ESMTP id A8E97FAB19 for ; Wed, 8 Jan 2014 05:13:04 -0800 (PST) Received: by mail-qe0-f46.google.com with SMTP id a11so1592724qen.5 for ; Wed, 08 Jan 2014 05:13:04 -0800 (PST) In-Reply-To: <1389186748-1954-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni LPT does have PCH refclk, but it's different form the IBX/CPT/PPT one and doesn't use the same structs. It is wrong to have a message saying that "LPT does not has PCH refclk" (sic). While at it, signal that we only want this function on IBX/CPT/PPT by renaming it and adding a WARN. On HSW we also print "0 shared PLLs initialized", but we *do* have shared PLLs on HSW (LCPLL, WRPLL, SPLL) and we *do* initialize them. We just don't use "struct intel_shared_dpll". So remove the debug message. In the future we may want to rename all that "intel shared pll" code to "ibx shared pll", but I'll leave this to another patch. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 034952c..df3cf69 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1211,15 +1211,12 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv, } } -static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) +static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) { u32 val; bool enabled; - if (HAS_PCH_LPT(dev_priv->dev)) { - DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); - return; - } + WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); val = I915_READ(PCH_DREF_CONTROL); enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | @@ -10067,7 +10064,7 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) { /* PCH refclock must be enabled first */ - assert_pch_refclk_enabled(dev_priv); + ibx_assert_pch_refclk_enabled(dev_priv); I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); @@ -10135,8 +10132,6 @@ static void intel_shared_dpll_init(struct drm_device *dev) dev_priv->num_shared_dpll = 0; BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); - DRM_DEBUG_KMS("%i shared PLLs initialized\n", - dev_priv->num_shared_dpll); } static void intel_crtc_init(struct drm_device *dev, int pipe) -- 1.8.4.2