From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 0/4] drm/i915: Small step towards atomic modeset Date: Mon, 13 Jan 2014 18:56:14 +0200 Message-ID: <1389632174.8261.48.camel@intelbox> References: <1389346089-18753-1-git-send-email-ville.syrjala@linux.intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1702443560==" Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 4E37711FCE0 for ; Mon, 13 Jan 2014 08:56:36 -0800 (PST) In-Reply-To: <1389346089-18753-1-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1702443560== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-FWRRnZCSdjJvmC9ltI8Q" --=-FWRRnZCSdjJvmC9ltI8Q Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 2014-01-10 at 11:28 +0200, ville.syrjala@linux.intel.com wrote: > From: Ville Syrj=C3=A4l=C3=A4 Looks ok to me. On the series: Reviewed-by: Imre Deak >=20 > I started to think a bit about how the code should look for doing a full > modeset for more than one pipe at a time. This is how far I got yesterday= . >=20 > I suppose the next thing would be moving the PLL calculations into comput= e > config stage, and then actually computing a new pipe config for more than > one pipe. >=20 > After that we could improve the IVB bifurcate stuff to handle cases where > pipe B is already enabled w/ > 2 FDI lanes, and then we try to light up > pipe C. Assuming pipe B bandwidth can be reduced sufficiently to fit into > two lanes, such an operation should succeed. >=20 > But I think I'll try to finish off some of my other pending stuff before > I continue with this. >=20 > I fired this up on an IVB briefly and things seem fine. I didn't actually > test the VLV cdclk change due to lack of hardware. >=20 > Ville Syrj=C3=A4l=C3=A4 (4): > drm/i915: Pre-compute pipe enabled state > drm/i915: Prepare to track new pipe config per pipe > drm/i915: Use new_config and new_enabled to simplify the VLV cdclk > code > drm/i915: Don't oops if the initial modeset fails >=20 > drivers/gpu/drm/i915/intel_display.c | 140 +++++++++++++++++++++++++++--= ------ > drivers/gpu/drm/i915/intel_drv.h | 3 + > 2 files changed, 111 insertions(+), 32 deletions(-) >=20 --=-FWRRnZCSdjJvmC9ltI8Q Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQEcBAABAgAGBQJS1BquAAoJEORIIAnNuWDFIZcH/2sEop+5KuobTO+aHaVJQA8B 3KbVrUkjTksewV3AdH03WKFhPRUktufAod2nXbM7GV6klvzlT97VZiRrbwQvRuA3 71mQ9dnsh5ID2n51XtIfw5bTI5IOm7oLcYTmy0VsegddEodCcPSVOm/xUfN+w+ep PbxnJoSl9ngr6WIwuQjryOhzvsjbnAuYvqeCENHmuuhcEUKfuqqxD73RMeECsFpL VwR2LeBcHOhv+GHtoIBga+7Tk2WrcbaU8dmg9acYQ0meNqpUvjHD/34PEna0wgrp T9aAA0bC8XDhftM3zpgSCtEQZRO8HU5ZIaNAkIg0ZSCHnJyQZ6YCB23uVs72oZI= =Ntsw -----END PGP SIGNATURE----- --=-FWRRnZCSdjJvmC9ltI8Q-- --===============1702443560== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1702443560==--