From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chia-I Wu Subject: [PATCH 1/2] drm/i915: enable HiZ Raw Stall Optimization on HSW Date: Tue, 28 Jan 2014 13:29:33 +0800 Message-ID: <1390886974-2530-1-git-send-email-olvaffe@gmail.com> References: <1390810716-13510-1-git-send-email-olvaffe@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ie0-f174.google.com (mail-ie0-f174.google.com [209.85.223.174]) by gabe.freedesktop.org (Postfix) with ESMTP id 4568B11D84A for ; Mon, 27 Jan 2014 21:29:45 -0800 (PST) Received: by mail-ie0-f174.google.com with SMTP id tp5so7094134ieb.33 for ; Mon, 27 Jan 2014 21:29:44 -0800 (PST) Received: from localhost.localdomain (122-116-175-74.HINET-IP.hinet.net. [122.116.175.74]) by mx.google.com with ESMTPSA id d18sm52821643igz.0.2014.01.27.21.29.41 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 27 Jan 2014 21:29:43 -0800 (PST) In-Reply-To: <1390810716-13510-1-git-send-email-olvaffe@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org From: Chia-I Wu The optimization is available on Ivy Bridge and later, and is disabled by default. Enabling it helps certain workloads such as GLBenchmark TRex test. No piglit regression. v2 - no need to save the register before suspend as init_clock_gating can correctly program it after resume - split IVB change to another commit Signed-off-by: Chia-I Wu --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 76126e0..c74bc28 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -934,6 +934,8 @@ #define ECO_GATING_CX_ONLY (1<<3) #define ECO_FLIP_DONE (1<<0) +#define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ +#define HIZ_RAW_STALL_OPT_DISABLE (1<<2) #define CACHE_MODE_1 0x7004 /* IVB+ */ #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d77cc81..c535e5c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4789,6 +4789,10 @@ static void haswell_init_clock_gating(struct drm_device *dev) /* WaVSRefCountFullforceMissDisable:hsw */ gen7_setup_fixed_func_scheduler(dev_priv); + /* enable HiZ Raw Stall Optimization */ + I915_WRITE(CACHE_MODE_0_GEN7, + _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); + /* WaDisable4x2SubspanOptimization:hsw */ I915_WRITE(CACHE_MODE_1, _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); -- 1.8.3.1