From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chia-I Wu Subject: [PATCH 2/2] drm/i915: enable HiZ Raw Stall Optimization on IVB Date: Tue, 28 Jan 2014 13:29:34 +0800 Message-ID: <1390886974-2530-2-git-send-email-olvaffe@gmail.com> References: <1390810716-13510-1-git-send-email-olvaffe@gmail.com> <1390886974-2530-1-git-send-email-olvaffe@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ie0-f178.google.com (mail-ie0-f178.google.com [209.85.223.178]) by gabe.freedesktop.org (Postfix) with ESMTP id C743E11D849 for ; Mon, 27 Jan 2014 21:29:47 -0800 (PST) Received: by mail-ie0-f178.google.com with SMTP id x13so6825787ief.23 for ; Mon, 27 Jan 2014 21:29:46 -0800 (PST) Received: from localhost.localdomain (122-116-175-74.HINET-IP.hinet.net. [122.116.175.74]) by mx.google.com with ESMTPSA id d18sm52821643igz.0.2014.01.27.21.29.44 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 27 Jan 2014 21:29:45 -0800 (PST) In-Reply-To: <1390886974-2530-1-git-send-email-olvaffe@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org From: Chia-I Wu The optimization helps IVB too. No piglit regression. Signed-off-by: Chia-I Wu --- drivers/gpu/drm/i915/intel_pm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index c535e5c..58aba3e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4881,6 +4881,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) /* WaVSRefCountFullforceMissDisable:ivb */ gen7_setup_fixed_func_scheduler(dev_priv); + /* enable HiZ Raw Stall Optimization */ + I915_WRITE(CACHE_MODE_0_GEN7, + _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); + /* WaDisable4x2SubspanOptimization:ivb */ I915_WRITE(CACHE_MODE_1, _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); -- 1.8.3.1