From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH] drm/i915: vlv: fix DP PHY lockup due to invalid PP sequencer setup Date: Thu, 30 Jan 2014 17:58:04 +0200 Message-ID: <1391097484.26112.2.camel@intelbox> References: <1391093442-16520-1-git-send-email-imre.deak@intel.com> <20140130155224.GU17001@phenom.ffwll.local> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0079762330==" Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 6BCB511F37F for ; Thu, 30 Jan 2014 07:58:27 -0800 (PST) In-Reply-To: <20140130155224.GU17001@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0079762330== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-UGIHiykPQx8oEbrxz0nq" --=-UGIHiykPQx8oEbrxz0nq Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 2014-01-30 at 16:52 +0100, Daniel Vetter wrote: > On Thu, Jan 30, 2014 at 04:50:42PM +0200, Imre Deak wrote: > > Atm we setup the HW panel power sequencer logic both for eDP and DP > > ports. On eDP we then go on and start the power on sequence and commenc= e > > with link training when it's ready. On DP we don't do the power on > > sequencing but do the link training immediately. At this point the DP > > PHY block gets stuck, since - supposedly - it is waiting for the power > > on sequence to finish. The actual register write that seems to hold off > > the PHY is PIPEX_PP_ON_DELAYS[Panel Control Port Select]. Writing here > > a non-0 value eventually sets PIPEX_PP_STATUS[Require Asset Status] to > > 1 and blocks the PHY until the panel power on is ready. > >=20 > > Fix this by not doing any PP sequencing setup for DP ports. > >=20 > > Thanks to Ville Syrj=C3=A4l=C3=A4, Jesse Barnes and Todd Previte for th= e help in > > tracking this down. > >=20 > > Signed-off-by: Imre Deak >=20 > Ah, the infamous ABCD hack we're using all over the place in intel_lvds.c= . > On edp we didn't have a need for it thus far since the "require asset > status" checks have all been fused of, with the PP being on the PCH and > the edp port on the north display block. If this is really all we need to > appease the hardware then I'm heavily in favour of it as opposed to > resurrect the ABCD hack for intel_dp.c. Yea, it seems it's not needed on BYT, since even with the PP_CONTROL being all 0 (and not doing any further PP sequencing setup) things work fine. > One thing though: Should we add a check for the "Required Asset Status" > bit somewhere? I don't really have a good idea for a spot to put this > into, hence the question. We could add it for eDP, but I guess based on the above for DP we don't need to check it. --Imre > -Daniel >=20 > > --- > > drivers/gpu/drm/i915/intel_dp.c | 10 ++++++---- > > 1 file changed, 6 insertions(+), 4 deletions(-) > >=20 > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/int= el_dp.c > > index ffac7e8..b744073 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -1933,10 +1933,12 @@ static void vlv_pre_enable_dp(struct intel_enco= der *encoder) > > =20 > > mutex_unlock(&dev_priv->dpio_lock); > > =20 > > - /* init power sequencer on this pipe and port */ > > - intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); > > - intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, > > - &power_seq); > > + if (is_edp(intel_dp)) { > > + /* init power sequencer on this pipe and port */ > > + intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); > > + intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, > > + &power_seq); > > + } > > =20 > > intel_enable_dp(encoder); > > =20 > > --=20 > > 1.8.4 > >=20 > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx >=20 --=-UGIHiykPQx8oEbrxz0nq Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQEcBAABAgAGBQJS6naMAAoJEORIIAnNuWDFQrUH/0Zu94vZiIbSNuCKUWXo2WQZ TcknJekcnaD2rnFurzmjVUCFApQFFiD/AEdvMRi77Cq35w7g4ItOCv49B6ypOPFE lxCh/tt64rdhqkggeALrYRpJDUKgaEJcwLmfHfNGV1gclXdyIxwplU14ZO4Py1Oy EI8j8qVRZ3NUxTbnOx1HNtL4RR7o0xCauCNZLeU8irIw5IyIGMjhvAeydUM3Pw4V YeYRnj2JB/dBaFR4nboq7VR26xOAhoUtvy67HMhFvvAilWDd/ynQ0otdoN0p9VJw iIG5/4ggGzw62u7fdYWy5GGBv0E4X2x1UngVGz0kgyFL4dd/SZxcl37o5d/t/6Q= =fISq -----END PGP SIGNATURE----- --=-UGIHiykPQx8oEbrxz0nq-- --===============0079762330== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0079762330==--