From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 7/5] drm/i915: Improve gen3/4 frame counter Date: Tue, 18 Feb 2014 16:16:00 +0200 Message-ID: <1392732960.13243.5.camel@intelbox> References: <1392306174-9148-1-git-send-email-ville.syrjala@linux.intel.com> <1392725061-30144-1-git-send-email-ville.syrjala@linux.intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0554331243==" Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 4EE69FAA6A for ; Tue, 18 Feb 2014 06:16:24 -0800 (PST) In-Reply-To: <1392725061-30144-1-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0554331243== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-XOZC2+Y2mFu1hZBUwb1o" --=-XOZC2+Y2mFu1hZBUwb1o Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2014-02-18 at 14:04 +0200, ville.syrjala@linux.intel.com wrote: > From: Ville Syrj=C3=A4l=C3=A4 >=20 > Currently the logic to fix up the frame counter on gen3/4 assumes that > start of vblank occurs at vblank_start*htotal pixels, when in fact > it occurs htotal-hsync_start pixels earlier. Apply the appropriate > adjustment to make the frame counter more accurate. >=20 > Also fix the vblank start position for interlaced display modes. >=20 > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/i915_irq.c | 21 ++++++++++++++++----- > 1 file changed, 16 insertions(+), 5 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_= irq.c > index 9f1c449..fc49fb6 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -639,7 +639,7 @@ static u32 i915_get_vblank_counter(struct drm_device = *dev, int pipe) > drm_i915_private_t *dev_priv =3D (drm_i915_private_t *) dev->dev_privat= e; > unsigned long high_frame; > unsigned long low_frame; > - u32 high1, high2, low, pixel, vbl_start; > + u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; > =20 > if (!i915_pipe_enabled(dev, pipe)) { > DRM_DEBUG_DRIVER("trying to get vblank count for disabled " > @@ -653,17 +653,28 @@ static u32 i915_get_vblank_counter(struct drm_devic= e *dev, int pipe) > const struct drm_display_mode *mode =3D > &intel_crtc->config.adjusted_mode; > =20 > - vbl_start =3D mode->crtc_vblank_start * mode->crtc_htotal; > + htotal =3D mode->crtc_htotal; > + hsync_start =3D mode->crtc_hsync_start; > + vbl_start =3D mode->crtc_vblank_start; > + if (mode->flags & DRM_MODE_FLAG_INTERLACE) > + vbl_start =3D DIV_ROUND_UP(vbl_start, 2); The adjustment for interlace mode is already done in drm_mode_setcrtc, so I think we don't need it here. Otherwise this patch makes sense to me based on the signal chart you drew on this, so: Reviewed-by: Imre Deak > } else { > enum transcoder cpu_transcoder =3D (enum transcoder) pipe; > - u32 htotal; > =20 > htotal =3D ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; > + hsync_start =3D (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1; > vbl_start =3D (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; > - > - vbl_start *=3D htotal; > + if ((I915_READ(PIPECONF(cpu_transcoder)) & > + PIPECONF_INTERLACE_MASK) !=3D PIPECONF_PROGRESSIVE) > + vbl_start =3D DIV_ROUND_UP(vbl_start, 2); > } > =20 > + /* Convert to pixel count */ > + vbl_start *=3D htotal; > + > + /* Start of vblank event occurs at start of hsync */ > + vbl_start -=3D htotal - hsync_start; > + > high_frame =3D PIPEFRAME(pipe); > low_frame =3D PIPEFRAMEPIXEL(pipe); > =20 --=-XOZC2+Y2mFu1hZBUwb1o Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTA2sgAAoJEORIIAnNuWDFx9YH/0LTe3PxqgQMzOp4mdCOMcuV Hzpy4ECDXahhNVkatQXjiWhPrAAPXrRaPQUl0be5EscfsEXzDHmlGqrx2XhccxH1 Ofu9G5DOrwMfiUPvPff7uvERQ0FvB03J3lmyW1RecbdtiJTRYllmy3Gsv59WYLM+ 8xVMDIzZiJwwAP4ei1IJS9vv8wSCYebo/rCQLgg4HP6JKIenhMSOzffIpI7HPCig hnVz8kAQKTSruO3Tv6sLlKqcNmMfbLBLCTpQLl2Re5VcKTI3ElhDWat6Ru500209 Tux6la2+fS6fiNTf0nIixKMzzEYF7sSs9voGCtL2XTwd8DTt+S6R7XMVwOQfwz0= =9RW5 -----END PGP SIGNATURE----- --=-XOZC2+Y2mFu1hZBUwb1o-- --===============0554331243== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0554331243==--