From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 7/5] drm/i915: Improve gen3/4 frame counter Date: Tue, 18 Feb 2014 17:11:18 +0200 Message-ID: <1392736278.13243.8.camel@intelbox> References: <1392306174-9148-1-git-send-email-ville.syrjala@linux.intel.com> <1392725061-30144-1-git-send-email-ville.syrjala@linux.intel.com> <1392732960.13243.5.camel@intelbox> <20140218144102.GT3852@intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0893062374==" Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 6684BFAB2D for ; Tue, 18 Feb 2014 07:11:41 -0800 (PST) In-Reply-To: <20140218144102.GT3852@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Ville =?ISO-8859-1?Q?Syrj=E4l=E4?= Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0893062374== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-Ynum/z9n0RQlyD86C0ho" --=-Ynum/z9n0RQlyD86C0ho Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2014-02-18 at 16:41 +0200, Ville Syrj=C3=A4l=C3=A4 wrote: > On Tue, Feb 18, 2014 at 04:16:00PM +0200, Imre Deak wrote: > > On Tue, 2014-02-18 at 14:04 +0200, ville.syrjala@linux.intel.com wrote: > > > From: Ville Syrj=C3=A4l=C3=A4 > > >=20 > > > Currently the logic to fix up the frame counter on gen3/4 assumes tha= t > > > start of vblank occurs at vblank_start*htotal pixels, when in fact > > > it occurs htotal-hsync_start pixels earlier. Apply the appropriate > > > adjustment to make the frame counter more accurate. > > >=20 > > > Also fix the vblank start position for interlaced display modes. > > >=20 > > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > > > --- > > > drivers/gpu/drm/i915/i915_irq.c | 21 ++++++++++++++++----- > > > 1 file changed, 16 insertions(+), 5 deletions(-) > > >=20 > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i= 915_irq.c > > > index 9f1c449..fc49fb6 100644 > > > --- a/drivers/gpu/drm/i915/i915_irq.c > > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > > @@ -639,7 +639,7 @@ static u32 i915_get_vblank_counter(struct drm_dev= ice *dev, int pipe) > > > drm_i915_private_t *dev_priv =3D (drm_i915_private_t *) dev->dev_pr= ivate; > > > unsigned long high_frame; > > > unsigned long low_frame; > > > - u32 high1, high2, low, pixel, vbl_start; > > > + u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; > > > =20 > > > if (!i915_pipe_enabled(dev, pipe)) { > > > DRM_DEBUG_DRIVER("trying to get vblank count for disabled " > > > @@ -653,17 +653,28 @@ static u32 i915_get_vblank_counter(struct drm_d= evice *dev, int pipe) > > > const struct drm_display_mode *mode =3D > > > &intel_crtc->config.adjusted_mode; > > > =20 > > > - vbl_start =3D mode->crtc_vblank_start * mode->crtc_htotal; > > > + htotal =3D mode->crtc_htotal; > > > + hsync_start =3D mode->crtc_hsync_start; > > > + vbl_start =3D mode->crtc_vblank_start; > > > + if (mode->flags & DRM_MODE_FLAG_INTERLACE) > > > + vbl_start =3D DIV_ROUND_UP(vbl_start, 2); > >=20 > > The adjustment for interlace mode is already done in drm_mode_setcrtc, > > so I think we don't need it here. >=20 > We throw away the values filled in by drm_mode_setcrtc(). Which is a > good thing since it rounds the result the wrong way (for our hardware > at least). The values we see here are filled in by > intel_modeset_pipe_config() which doesn't pass the > CRTC_INTERLACE_HALVE_V flag to drm_mode_set_crtcinfo(). Ah, true, I see now. This looks also ok then. --Imre > > Otherwise this patch makes sense to me > > based on the signal chart you drew on this, so: > >=20 > > Reviewed-by: Imre Deak > >=20 > > > } else { > > > enum transcoder cpu_transcoder =3D (enum transcoder) pipe; > > > - u32 htotal; > > > =20 > > > htotal =3D ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + = 1; > > > + hsync_start =3D (I915_READ(HSYNC(cpu_transcoder)) & 0x1fff) + 1; > > > vbl_start =3D (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; > > > - > > > - vbl_start *=3D htotal; > > > + if ((I915_READ(PIPECONF(cpu_transcoder)) & > > > + PIPECONF_INTERLACE_MASK) !=3D PIPECONF_PROGRESSIVE) > > > + vbl_start =3D DIV_ROUND_UP(vbl_start, 2); > > > } > > > =20 > > > + /* Convert to pixel count */ > > > + vbl_start *=3D htotal; > > > + > > > + /* Start of vblank event occurs at start of hsync */ > > > + vbl_start -=3D htotal - hsync_start; > > > + > > > high_frame =3D PIPEFRAME(pipe); > > > low_frame =3D PIPEFRAMEPIXEL(pipe); > > > =20 > >=20 >=20 >=20 >=20 --=-Ynum/z9n0RQlyD86C0ho Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTA3gWAAoJEORIIAnNuWDFTKkIALYler/og9g3SGS6DHDAJTg0 cnAAqZLFpfGxB1QN5eCNiNZCmzr80NAMSzBy89IVSLoQyxe17p2xxCfuGmm9PQCs AMUdArstCxnJaod8lFvIccj7iBgmRR5zTYuliwp+Afgq07G1Ykb2IliVDEwDoQIn LFsz13ysDOndtz8M+do9bG0eRH3KvPc/Y34oSQV9LhR2PRCKveCa2P99lmJrT8cx PPaU0dEt2bFmu2Zg1e7sgmHSqsrne+98MFDVGVqhq/YObmiRJR/jcC/ou3TkOJ4L 2FX4O3k7S1L89AxCaIrQ2KPrFUJwY4y5mkGP+/g8haRjvy47en3OgQbKs29w+9A= =W8HH -----END PGP SIGNATURE----- --=-Ynum/z9n0RQlyD86C0ho-- --===============0893062374== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0893062374==--