From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 04/11] drm/i915: get runtime PM at intel_set_mode Date: Mon, 24 Feb 2014 13:23:40 +0200 Message-ID: <1393241020.13131.22.camel@intelbox> References: <1393001548-2883-1-git-send-email-przanoni@gmail.com> <1393001548-2883-5-git-send-email-przanoni@gmail.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1044038279==" Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id B4B94FA9D0 for ; Mon, 24 Feb 2014 03:24:53 -0800 (PST) In-Reply-To: <1393001548-2883-5-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org --===============1044038279== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-YEBoYqmSkSOEJfLB2eHj" --=-YEBoYqmSkSOEJfLB2eHj Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 2014-02-21 at 13:52 -0300, Paulo Zanoni wrote: > From: Paulo Zanoni >=20 > Otherwise, when we run intel_modeset_check_state we may already be > runtime suspended, and our state checking code will read registers > while the device is suspended. This can only happen if your > autosuspend_delay_ms is low (not the default 10s). >=20 > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_display.c | 5 +++++ > 1 file changed, 5 insertions(+) >=20 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 10ec401..c64fb7f 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -9746,13 +9746,18 @@ static int intel_set_mode(struct drm_crtc *crtc, > struct drm_display_mode *mode, > int x, int y, struct drm_framebuffer *fb) > { > + struct drm_device *dev =3D crtc->dev; > + struct drm_i915_private *dev_priv =3D dev->dev_private; > int ret; > =20 > + intel_runtime_pm_get(dev_priv); > + > ret =3D __intel_set_mode(crtc, mode, x, y, fb); > =20 > if (ret =3D=3D 0) > intel_modeset_check_state(crtc->dev); > =20 > + intel_runtime_pm_put(dev_priv); > return ret; > } Ideally these should be done as part of a power domain get/put as some platforms will need to turn on some power wells too and on that path we do anyway a runtime PM get/put. In the latest VLV power domain support patchset [1] I added the power domain get/put and state check to places I thought necessary. I haven't tested it on HSW but afaics the ones added for the HW state readout code would solve the issue you describe here. --Imre [1] http://www.spinics.net/lists/intel-gfx/msg40344.html --=-YEBoYqmSkSOEJfLB2eHj Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTCyu8AAoJEORIIAnNuWDFeb8H/0bPr7UdnclI+xr/49sV6CzO qU+r4bxDWhNbvYbVSu+sGig0PMr4wy4ow7SN5AA8DOggVYukOoiIuOVqWdHQOT2y qlVGgPF2iEOvicbOAnvdM/+St2ipOcEQXLEAj5ZzHiFaeZiagowQWhciMUfor5RC 4wholloB+lmangnbyuRIx0zRFhRDBJ3SvQulKCQzv/RpPkOjXEm16uNge3obiTjw RkZqGKIBpqY1UAxhS8TGYa6gXp5p7MJegGxp+oN43e2QFWzKRoTuC0bstfg0wZoz BAiD9Rbodv3YIhOgXlyZmVVCNR+r5kIaoQGWinkcEa1EwXQXj1HSzLJbm47xyT4= =FQI+ -----END PGP SIGNATURE----- --=-YEBoYqmSkSOEJfLB2eHj-- --===============1044038279== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1044038279==--