From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 12/19] drm/i915: sanitize PUNIT register macro definitions Date: Mon, 24 Feb 2014 15:12:47 +0200 Message-ID: <1393247567.13131.80.camel@intelbox> References: <1392674540-10915-1-git-send-email-imre.deak@intel.com> <1392674540-10915-13-git-send-email-imre.deak@intel.com> <20140220114614.5d49e141@jbarnes-desktop> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0095014470==" Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id B2747FAA60 for ; Mon, 24 Feb 2014 05:12:49 -0800 (PST) In-Reply-To: <20140220114614.5d49e141@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0095014470== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-ocuVKkheHJR3DJmcZt8j" --=-ocuVKkheHJR3DJmcZt8j Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 2014-02-20 at 11:46 -0800, Jesse Barnes wrote: > On Tue, 18 Feb 2014 00:02:13 +0200 > Imre Deak wrote: >=20 > > In the upcoming patches we'll need to access the rest of the fields in > > the punit power gating register, so prepare for that. > >=20 > > Signed-off-by: Imre Deak > > --- > > drivers/gpu/drm/i915/i915_reg.h | 29 +++++++++++++++++++++++------ > > drivers/gpu/drm/i915/intel_uncore.c | 4 +++- > > 2 files changed, 26 insertions(+), 7 deletions(-) > >=20 > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index 2f564ce..5a700e9 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -377,14 +377,31 @@ > > #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) > > #define DSPFREQGUAR_SHIFT 14 > > #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) > > + > > +enum punit_power_well { > > + PUNIT_POWER_WELL_RENDER =3D 0, > > + PUNIT_POWER_WELL_MEDIA =3D 1, > > + PUNIT_POWER_WELL_DISP2D =3D 3, > > + PUNIT_POWER_WELL_DPIO_CMN_BC =3D 5, > > + PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 =3D 6, > > + PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 =3D 7, > > + PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 =3D 8, > > + PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 =3D 9, > > + PUNIT_POWER_WELL_DPIO_RX0 =3D 10, > > + PUNIT_POWER_WELL_DPIO_RX1 =3D 11, > > + PUNIT_POWER_WELL_DPIO_RX2 =3D 12, > > + PUNIT_POWER_WELL_DPIO_RX3 =3D 13, > > + > > + PUNIT_POWER_WELL_NUM, > > +}; > > + > > #define PUNIT_REG_PWRGT_CTRL 0x60 > > #define PUNIT_REG_PWRGT_STATUS 0x61 > > -#define PUNIT_CLK_GATE 1 > > -#define PUNIT_PWR_RESET 2 > > -#define PUNIT_PWR_GATE 3 > > -#define RENDER_PWRGT (PUNIT_PWR_GATE << 0) > > -#define MEDIA_PWRGT (PUNIT_PWR_GATE << 2) > > -#define DISP2D_PWRGT (PUNIT_PWR_GATE << 6) > > +#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) > > +#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2)) > > +#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2)) > > +#define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2)) > > +#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2)) > > =20 > > #define PUNIT_REG_GPU_LFM 0xd3 > > #define PUNIT_REG_GPU_FREQ_REQ 0xd4 > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915= /intel_uncore.c > > index c628414..4aab7c2 100644 > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > @@ -354,7 +354,9 @@ void intel_uncore_sanitize(struct drm_device *dev) > > mutex_lock(&dev_priv->rps.hw_lock); > > reg_val =3D vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS); > > =20 > > - if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT)) > > + if (reg_val & (PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_RENDER) | > > + PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_MEDIA) | > > + PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_DISP2D))) > > vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0); > > =20 > > mutex_unlock(&dev_priv->rps.hw_lock); >=20 > I'd like to see a doc reference here, as I never remember which one has > these bits... It's the PUNIT 0.8 HAS, will add a comment about it here. > Also, are you sure about the RX bits? The > PUNIT_HAS_0.8 doc says only subsystems 10-11 cover RX, maybe in a ganged > config? You're right, I overlooked this, there are only 2 RX lanes. We don't use them atm, but we'll still need to disable those wells. I'll fix this up. --Imre >=20 > Otherwise: > Reviewed-by: Jesse Barnes >=20 --=-ocuVKkheHJR3DJmcZt8j Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTC0VPAAoJEORIIAnNuWDFDi8IAOQhPa2HGHkgngp6pDRAWnS/ 1Qd815Ek1rvGOfN8YG4/zUr3nxtEhmtJSC20yiOOYQIwH1w1Fns9VaxhmeM//fRS xhkjMzxFBEviWEZa+WHEIBCuOPuu/9wRtQhz2wbcTsEIilgym9E2RTPDe3TZxzkk FrOKRJJFFJoRoiERuGMmMqcVFbVO64keV/mXpWsgm8ehTf9fzGT+ywx2hJHdeFlX vAjCize+BZBOIi0OxN4r6zxS7uVDELasdN3Hzs1epxiIeb4Q7ifsVZ0ylmowsnRn ktu5jCx7SxtwkJMR9Di9sdBawruw3avscxomej0U7utPIc4Yv7gNLTouY/KnApM= =vD3O -----END PGP SIGNATURE----- --=-ocuVKkheHJR3DJmcZt8j-- --===============0095014470== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0095014470==--