From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 10/23] drm/i915: get/put runtime PM when we get/put a power domain Date: Fri, 28 Feb 2014 17:45:54 +0200 Message-ID: <1393602354.3479.78.camel@intelbox> References: <1393540010-1582-1-git-send-email-przanoni@gmail.com> <1393540010-1582-11-git-send-email-przanoni@gmail.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0246774589==" Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 1BDC7FA537 for ; Fri, 28 Feb 2014 07:45:58 -0800 (PST) In-Reply-To: <1393540010-1582-11-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org --===============0246774589== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-14q9FveX5XYEM3Rj/PJH" --=-14q9FveX5XYEM3Rj/PJH Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 2014-02-27 at 19:26 -0300, Paulo Zanoni wrote: > From: Paulo Zanoni >=20 > Any power domain will require the HW to be in PCI D0 state, so just do > the simple thing. >=20 > Dear maintainer: since intel_display_power_put() and > intel_display_power_get() are almost identical, git-am has failed to > apply the patch on my local machine once: it added both chunks to > put(), instead of one chunk to get() and another to put(). When you > apply this patch to your tree, please check if it is correct. >=20 > v2: - Add the warning above. >=20 > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_pm.c | 4 ++++ > 1 file changed, 4 insertions(+) >=20 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index d68fee2..772aa678 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5341,6 +5341,8 @@ void intel_display_power_get(struct drm_device *dev= , > struct i915_power_well *power_well; > int i; > =20 > + intel_runtime_pm_get(dev_priv); > + > power_domains =3D &dev_priv->power_domains; > =20 > mutex_lock(&power_domains->lock); > @@ -5372,6 +5374,8 @@ void intel_display_power_put(struct drm_device *dev= , > __intel_power_well_put(dev, power_well); > =20 > mutex_unlock(&power_domains->lock); > + > + intel_runtime_pm_put(dev_priv); > } I'd prefer to have these in the power_well->enable/disable handlers after applying the VLV power domains patchset. That way we would have the whole power well enable/disable sequence laid out in the same function and avoid going towards a middle-ware like approach. But this is ok, if we apply this patchset first. In that case: Reviewed-by: Imre Deak > =20 > static struct i915_power_domains *hsw_pwr; --=-14q9FveX5XYEM3Rj/PJH Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTEK8yAAoJEORIIAnNuWDFsvsIAKlJqhZZg+WwTT7Vfvy8QgcD cgJaAMPuPrrBIE9kH0HRM8WqkzmRMHwRrngI5wNlASgzVXCPBq/9O0t5vANZIGXh ZiTUxwrjiqdMTokd7bVjEUfcJK760RJeNFcSy7qo6YjhBTRTpPPxRMZrnaYcg7hK rIiUikG3bxEVXfbe95GmDqzwqZ1bBDO8MrMpXoSDtw8YanLNL7epREHRifH4WTHf AcqRLJyHaJW4Fn/JVBF+LsyZH40UFLRIIunYadfKsyDU6GtOJKJmc5RdwYBPZ2nA kPIoTss0mAZHsF9Nl3Gol87PUeX/ufXQ96m5xlqqR4ZyuaTr72uxEl5GHvDzMxg= =rLqf -----END PGP SIGNATURE----- --=-14q9FveX5XYEM3Rj/PJH-- --===============0246774589== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0246774589==--