From mboxrd@z Thu Jan 1 00:00:00 1970 From: sourab.gupta@intel.com Subject: [PATCH 0/6] Rendering Specific HW Workarounds for VLV Date: Mon, 24 Mar 2014 23:00:01 +0530 Message-ID: <1395682207-7092-1-git-send-email-sourab.gupta@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id EB4BE6EB27 for ; Mon, 24 Mar 2014 10:29:34 -0700 (PDT) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: Daniel Vetter , Sourab Gupta List-Id: intel-gfx@lists.freedesktop.org From: Sourab Gupta This patch series adds rendering specific HW workarounds for VLV platform. These patches leads to stable behavior on VLV, especially when playing 3D Apps, benchmarks. This patch series consolidates the earlier patch set in a clean thread and adds the in-patch changelogs which we had missed out earlier. The comments received on earlier patches are addressed. Akash Goel (6): drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore' drm/i915/vlv: Added a rendering specific Hw WA 'WaSendDummy3dPrimitveAfterSetContext' drm/i915: Enabling the TLB invalidate bit in GFX Mode register drm/i915/vlv: Remove the enabling of VS_TIMER_DISPATCH bit in MI MODE reg drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush' drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv drivers/gpu/drm/i915/i915_gem_context.c | 54 +++++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 4 +++ drivers/gpu/drm/i915/intel_pm.c | 10 ++++-- drivers/gpu/drm/i915/intel_ringbuffer.c | 39 ++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + 5 files changed, 102 insertions(+), 6 deletions(-) -- 1.8.5.1