From mboxrd@z Thu Jan 1 00:00:00 1970 From: sourab.gupta@intel.com Subject: [PATCH v4 1/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore' Date: Mon, 24 Mar 2014 23:00:02 +0530 Message-ID: <1395682207-7092-2-git-send-email-sourab.gupta@intel.com> References: <1395682207-7092-1-git-send-email-sourab.gupta@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id A0E2A6EB2F for ; Mon, 24 Mar 2014 10:29:37 -0700 (PDT) In-Reply-To: <1395682207-7092-1-git-send-email-sourab.gupta@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: Daniel Vetter , Akash Goel , Sourab Gupta List-Id: intel-gfx@lists.freedesktop.org From: Akash Goel Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'. In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI Store data commands. v2: Modified the WA comment (Ville) v3: Added the vlv identifier with WA name (Damien) v4: Reworked based on Chris' comments (WA moved to gen7 ring flush func, sending 6 dwords instead of 8) Signed-off-by: Sourab Gupta Signed-off-by: Akash Goel --- drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 87d1a2d..75cac4e 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -309,6 +309,29 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, u32 scratch_addr = ring->scratch.gtt_offset + 128; int ret; + if (invalidate_domains && IS_VALLEYVIEW(ring->dev)) { + /* + * WaTlbInvalidateStoreDataBefore:vlv + * This workaround is applicable in case the flush call has + * arrived in context of invalidate_all_caches function. + * Before pipecontrol with TLB invalidate set, need 2 store + * data commands (such as MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) + * Without this, hardware cannot guarantee the command after the + * PIPE_CONTROL with TLB inv will not use the old TLB values. + * FIXME: should apply to snb, ivb + */ + int i; + ret = intel_ring_begin(ring, 3 * 2); + if (ret) + return ret; + for (i = 0; i < 2; i++) { + intel_ring_emit(ring, MI_STORE_DWORD_INDEX); + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR); + intel_ring_emit(ring, 0); + } + intel_ring_advance(ring); + } + /* * Ensure that any following seqno writes only happen when the render * cache is indeed flushed. -- 1.8.5.1