From mboxrd@z Thu Jan 1 00:00:00 1970 From: sourab.gupta@intel.com Subject: [PATCH 4/6] drm/i915/vlv: Remove the enabling of VS_TIMER_DISPATCH bit in MI MODE reg Date: Mon, 24 Mar 2014 23:00:05 +0530 Message-ID: <1395682207-7092-5-git-send-email-sourab.gupta@intel.com> References: <1395682207-7092-1-git-send-email-sourab.gupta@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 5ED2D6EB27 for ; Mon, 24 Mar 2014 10:30:21 -0700 (PDT) In-Reply-To: <1395682207-7092-1-git-send-email-sourab.gupta@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: Daniel Vetter , Akash Goel List-Id: intel-gfx@lists.freedesktop.org From: Akash Goel Removing the VS_TIMER_DISPATCH bit enable for MI MODE reg for VLV platform as it is not required. Signed-off-by: Akash Goel --- drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index eb4811a..1512a71 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -599,7 +599,10 @@ static int init_render_ring(struct intel_ring_buffer *ring) int ret = init_ring_common(ring); if (INTEL_INFO(dev)->gen > 3) - I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); + /* FIXME, should also apply to ivb */ + if (!IS_VALLEYVIEW(dev)) + I915_WRITE(MI_MODE, + _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); /* We need to disable the AsyncFlip performance optimisations in order * to use MI_WAIT_FOR_EVENT within the CS. It should already be -- 1.8.5.1