From mboxrd@z Thu Jan 1 00:00:00 1970 From: sourab.gupta@intel.com Subject: [PATCH v2 5/6] drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush' Date: Mon, 24 Mar 2014 23:00:06 +0530 Message-ID: <1395682207-7092-6-git-send-email-sourab.gupta@intel.com> References: <1395682207-7092-1-git-send-email-sourab.gupta@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 3F2BA6EB37 for ; Mon, 24 Mar 2014 10:30:23 -0700 (PDT) In-Reply-To: <1395682207-7092-1-git-send-email-sourab.gupta@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: Daniel Vetter , Akash Goel , Sourab Gupta List-Id: intel-gfx@lists.freedesktop.org From: Akash Goel In Valleyview, Operational flush cannot be enabled on BWG A0 [Errata BWT006] v2: Corrected the code regarding the wrong usage of MASKED_BIT_DISABLE (Chris) Signed-off-by: Akash Goel Signed-off-by: Sourab Gupta --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b922e38..266bfa1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -972,6 +972,9 @@ enum punit_power_well { #define ECO_GATING_CX_ONLY (1<<3) #define ECO_FLIP_DONE (1<<0) +#define GEN7_CACHE_MODE_0 0x07000 /* IVB+ only */ +#define GEN7_RC_OP_FLUSH_ENABLE (1<<0) + #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ #define HIZ_RAW_STALL_OPT_DISABLE (1<<2) #define CACHE_MODE_1 0x7004 /* IVB+ */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index fd68f93..c3a8554 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5068,6 +5068,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev) _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); + /* WaDisable_RenderCache_OperationalFlush:vlv */ + I915_WRITE(GEN7_CACHE_MODE_0, _MASKED_BIT_DISABLE(GEN7_RC_OP_FLUSH_ENABLE)); + /* WaForceL3Serialization:vlv */ I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & ~L3SQ_URB_READ_CAM_MATCH_DISABLE); -- 1.8.5.1