From mboxrd@z Thu Jan 1 00:00:00 1970 From: sourab.gupta@intel.com Subject: [PATCH v2 4/6] drm/i915/vlv: Remove the enabling of VS_TIMER_DISPATCH bit in MI MODE reg Date: Mon, 24 Mar 2014 23:58:22 +0530 Message-ID: <1395685702-8070-1-git-send-email-sourab.gupta@intel.com> References: <20140324180116.GS4366@nuc-i3427.alporthouse.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A1666EB9E for ; Mon, 24 Mar 2014 11:27:55 -0700 (PDT) In-Reply-To: <20140324180116.GS4366@nuc-i3427.alporthouse.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: Daniel Vetter , Akash Goel , Sourab Gupta List-Id: intel-gfx@lists.freedesktop.org From: Akash Goel Removing the VS_TIMER_DISPATCH bit enable for MI MODE reg for Gen7 platform as it is not required. v2: Enhancing the scope of the patch to full Gen7 (Chris) Signed-off-by: Akash Goel Signed-off-by: Sourab Gupta Tested-by: Chris Wilson # ivb, hsw -Chris --- drivers/gpu/drm/i915/intel_ringbuffer.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index eb4811a..9983802 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -599,7 +599,9 @@ static int init_render_ring(struct intel_ring_buffer *ring) int ret = init_ring_common(ring); if (INTEL_INFO(dev)->gen > 3) - I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); + if (!IS_GEN7(dev)) + I915_WRITE(MI_MODE, + _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); /* We need to disable the AsyncFlip performance optimisations in order * to use MI_WAIT_FOR_EVENT within the CS. It should already be -- 1.8.5.1