From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 5/6] drm/i915: BDW needs D_COMP writes through MCHBAR Date: Tue, 01 Apr 2014 18:49:10 +0300 Message-ID: <1396367350.18070.45.camel@intelbox> References: <1394233957-3904-1-git-send-email-przanoni@gmail.com> <1394233957-3904-6-git-send-email-przanoni@gmail.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1893438770==" Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 066FF6E793 for ; Tue, 1 Apr 2014 08:53:28 -0700 (PDT) In-Reply-To: <1394233957-3904-6-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org --===============1893438770== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-ORI+qJesKtDq0V1ehtpk" --=-ORI+qJesKtDq0V1ehtpk Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 2014-03-07 at 20:12 -0300, Paulo Zanoni wrote: > From: Paulo Zanoni >=20 > That's what the spec said! And HSW needs it through pcode (you can > only read it through MCHBAR), so create hsw_write_dcomp to abstract > the weirdness. >=20 > Signed-off-by: Paulo Zanoni Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/intel_display.c | 28 ++++++++++++++++++---------- > 1 file changed, 18 insertions(+), 10 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index d6092be..2be4129 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6664,6 +6664,22 @@ static void assert_can_disable_lcpll(struct drm_i9= 15_private *dev_priv) > spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); > } > =20 > +static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t = val) > +{ > + struct drm_device *dev =3D dev_priv->dev; > + > + if (IS_HASWELL(dev)) { > + mutex_lock(&dev_priv->rps.hw_lock); > + if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, > + val)) > + DRM_ERROR("Failed to disable D_COMP\n"); > + mutex_unlock(&dev_priv->rps.hw_lock); > + } else { > + I915_WRITE(D_COMP, val); > + } > + POSTING_READ(D_COMP); > +} > + > /* > * This function implements pieces of two sequences from BSpec: > * - Sequence for display software to disable LCPLL > @@ -6701,11 +6717,7 @@ static void hsw_disable_lcpll(struct drm_i915_priv= ate *dev_priv, > =20 > val =3D I915_READ(D_COMP); > val |=3D D_COMP_COMP_DISABLE; > - mutex_lock(&dev_priv->rps.hw_lock); > - if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) > - DRM_ERROR("Failed to disable D_COMP\n"); > - mutex_unlock(&dev_priv->rps.hw_lock); > - POSTING_READ(D_COMP); > + hsw_write_dcomp(dev_priv, val); > ndelay(100); > =20 > if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) =3D=3D 0, 1= )) > @@ -6760,11 +6772,7 @@ static void hsw_restore_lcpll(struct drm_i915_priv= ate *dev_priv) > val =3D I915_READ(D_COMP); > val |=3D D_COMP_COMP_FORCE; > val &=3D ~D_COMP_COMP_DISABLE; > - mutex_lock(&dev_priv->rps.hw_lock); > - if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) > - DRM_ERROR("Failed to enable D_COMP\n"); > - mutex_unlock(&dev_priv->rps.hw_lock); > - POSTING_READ(D_COMP); > + hsw_write_dcomp(dev_priv, val); > =20 > val =3D I915_READ(LCPLL_CTL); > val &=3D ~LCPLL_PLL_DISABLE; --=-ORI+qJesKtDq0V1ehtpk Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTOt/2AAoJEORIIAnNuWDFyx8IAMyk8c7n4uWDUYvT1ozpTPz5 gOV/UOjmqDOd/O4Gp1VLrALmw2IKTZM2YUClQ7BZzeqRFSk0GWi4WWhvTZJ6NCQl r7nFVqvwqtLostKgdtHI/k1aMEQhbPeelnuNqV0GeLZxiRNxCq9CacCjKV9blfi7 qZDxid9+w8/5IGJo1JQ1t/kpfPIO/t7oNORFbQbde+VD4UGrVQf62uQh1LQJnEk7 3iipW+xue4WDh/O0YnSCHJhw3cEUue/G/ub3XaFw7CpyuJUu6IfObkhp7ZuA6RIT Nv65IfFjXvlaZpLZslc790+79lLoF/XCvgx4DXned+rUup6fH4Gv9fYZJ7vYVqA= =aAKH -----END PGP SIGNATURE----- --=-ORI+qJesKtDq0V1ehtpk-- --===============1893438770== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1893438770==--