From mboxrd@z Thu Jan 1 00:00:00 1970 From: Todd Previte Subject: [PATCH 3/5] drm/i915: Displayport - Add function to enable/disable scrambling on the main link Date: Tue, 8 Apr 2014 10:47:41 -0700 Message-ID: <1396979263-3245-4-git-send-email-tprevite@gmail.com> References: <1396979263-3245-1-git-send-email-tprevite@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-pb0-f42.google.com (mail-pb0-f42.google.com [209.85.160.42]) by gabe.freedesktop.org (Postfix) with ESMTP id DAC846E4E7 for ; Tue, 8 Apr 2014 10:48:08 -0700 (PDT) Received: by mail-pb0-f42.google.com with SMTP id rr13so1363912pbb.1 for ; Tue, 08 Apr 2014 10:48:08 -0700 (PDT) In-Reply-To: <1396979263-3245-1-git-send-email-tprevite@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Adds a function to enable and disable scrambling directly for the main link. This is functionality required to establish more fine-grained control over the Displayport interface, both for operational reliability and compliance testing. Signed-off-by: Todd Previte --- drivers/gpu/drm/i915/intel_dp.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index c865c32..1209de8 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2372,6 +2372,33 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) *DP = (*DP & ~mask) | signal_levels; } +void intel_dp_scrambler_disable(bool disable, struct intel_dp *intel_dp) +{ + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = intel_dig_port->base.base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + // SNB is 0x40000. ILK is 0x4400 + // IVB is 0x64000, HSW+ is 0x64040/0x64140 + uint32_t ctrl_reg, reg_value; + + if (HAS_DDI(dev)) + ctrl_reg = DP_TP_CTL(intel_dig_port->port); + else + ctrl_reg = intel_dp->output_reg; + + reg_value = I915_READ(ctrl_reg); + + // Scrambling is bit 7 (scrambling on == 0) + if (disable) + reg_value |= DP_TP_CTL_SCRAMBLE_DISABLE; + else + reg_value &= ~DP_TP_CTL_SCRAMBLE_DISABLE; + + I915_WRITE(ctrl_reg, reg_value); + POSTING_READ(ctrl_reg); +} + bool intel_dp_verify_link_status(DPLinkTrainingState state, uint8_t lane_count, -- 1.8.3.2