From mboxrd@z Thu Jan 1 00:00:00 1970 From: Todd Previte Subject: [PATCH 5/5] drm/i915: Displayport - Add function to execute a single iteration of channel equalization Date: Tue, 8 Apr 2014 10:47:43 -0700 Message-ID: <1396979263-3245-6-git-send-email-tprevite@gmail.com> References: <1396979263-3245-1-git-send-email-tprevite@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-pb0-f41.google.com (mail-pb0-f41.google.com [209.85.160.41]) by gabe.freedesktop.org (Postfix) with ESMTP id A2A7C6E4B4 for ; Tue, 8 Apr 2014 10:48:18 -0700 (PDT) Received: by mail-pb0-f41.google.com with SMTP id jt11so1359757pbb.28 for ; Tue, 08 Apr 2014 10:48:18 -0700 (PDT) In-Reply-To: <1396979263-3245-1-git-send-email-tprevite@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Adds a function to execute a single iteration of the channel equalization sequence for Displayport. This is functionality required to establish more fine-grained control over the Displayport interface, both for operational reliability and compliance testing. Signed-off-by: Todd Previte --- drivers/gpu/drm/i915/intel_dp.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 6baa26c..66dbda6 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2878,6 +2878,37 @@ exit: return clock_recovery_status; } +uint32_t intel_dp_exec_channel_equalization(struct intel_dp *intel_dp) +{ + uint32_t channel_equalization_status = DP_CHANNEL_EQUALIZATION_FAILED; + uint8_t link_status[DP_LINK_STATUS_SIZE]; + + // Set the correct training pattern + if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12) + intel_dp_set_training_pattern(DP_TRAINING_PATTERN_2, intel_dp); + else + intel_dp_set_training_pattern(DP_TRAINING_PATTERN_2, intel_dp); + + // Wait for channel equalization time period to expire + drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); + + // Check link status + if (!intel_dp_get_link_status(intel_dp, link_status)) { + channel_equalization_status = DP_LINK_STATUS_READ_FAILED; + goto exit; + } + + // Verify that both CR is still valid and CE is successful + if (intel_dp_verify_link_status(DP_LINK_TRAINING_STATE_CLOCK_REC, + intel_dp->lane_count, link_status) && + intel_dp_verify_link_status(DP_LINK_TRAINING_STATE_CHANNEL_EQ, + intel_dp->lane_count, link_status)) + channel_equalization_status = DP_CHANNEL_EQUALIZATION_COMPLETE; + +exit: + return channel_equalization_status; +} + static void intel_dp_link_down(struct intel_dp *intel_dp) { -- 1.8.3.2