[PATCH 0/7] Updated MIPI sequence for BYT

[Shobhit Kumar <shobhit.kumar@intel.com>]

Hi,
The changes in DSI sequence are as suggested by HW and SV teams. Notable
difference apart form few WAs is that for MIPI it is suggetsed that the
PORT is enabled before PIPE and PLANE. The patch makes these changes.
So few sequence changes, few workarounds and few new feature support like
Clockstop.

A generic panel driver to enable MIPI is planned in next patchset

Known issue - 
Today the upstream kernel does not have PMIC driver amd these patches works if 
UEFI BIOS enables MIPI and reuse  BKL_EN, PANEL_EN from there, but during
suspend/resume things will still fail.

Regards
Shobhit

Shobhit Kumar (7):
  drm/i915: Program Rcomp and band gap reset everytime we resume from power gate
  drm/i915: Enable MIPI port before the plane and pipe enable
  drm/i915: Disable DPOunit clock gating
  drm/i915: Parameterize the Clockstop and escape_clk_div
  drm/i915: Panel commands can be sent only when clock is in LP11
  drm/i915: Send DPI command explicitely in LP mode
  drm/i915: Enable RANDOM resolution support for MIPI panels

 drivers/gpu/drm/i915/intel_dsi.c     | 125 +++++++++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_dsi.h     |   4 +-
 drivers/gpu/drm/i915/intel_dsi_cmd.c |   4 +-
 drivers/gpu/drm/i915/intel_dsi_cmd.h |   5 +-
 4 files changed, 108 insertions(+), 30 deletions(-)

-- 
1.8.3.2