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From: Shobhit Kumar <shobhit.kumar@intel.com>
To: intel-gfx <intel-gfx@lists.freedesktop.org>
Cc: Jani Nikula <jani.nikula@intel.com>,
	Daniel Vetter <daniel.vetter@intel.com>
Subject: [PATCH 4/7] drm/i915: Parameterize the Clockstop and escape_clk_div
Date: Wed,  9 Apr 2014 13:59:33 +0530	[thread overview]
Message-ID: <1397032176-11988-5-git-send-email-shobhit.kumar@intel.com> (raw)
In-Reply-To: <1397032176-11988-1-git-send-email-shobhit.kumar@intel.com>

In preparation for Generic driver

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 11 +++++++++--
 drivers/gpu/drm/i915/intel_dsi.h |  4 +++-
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4793a5b..dfcdb10 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -495,10 +495,17 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
 	/* dphy stuff */
 
 	/* in terms of low power clock */
-	I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(ESCAPE_CLOCK_DIVIDER_1, 100));
+	I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100));
+
+	val = 0;
+	if (intel_dsi->eotp_pkt == 0)
+		val |= EOT_DISABLE;
+
+	if (intel_dsi->clock_stop)
+		val |= CLOCKSTOP;
 
 	/* recovery disables */
-	I915_WRITE(MIPI_EOT_DISABLE(pipe), intel_dsi->eot_disable);
+	I915_WRITE(MIPI_EOT_DISABLE(pipe), val);
 
 	/* in terms of txbyteclkhs. actual high to low switch +
 	 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index b4a27ce..550714c 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -95,8 +95,10 @@ struct intel_dsi {
 	u32 video_mode_format;
 
 	/* eot for MIPI_EOT_DISABLE register */
-	u32 eot_disable;
+	u8 eotp_pkt;
+	u8 clock_stop;
 
+	u8 escape_clk_div;
 	u32 port_bits;
 	u32 bw_timer;
 	u32 dphy_reg;
-- 
1.8.3.2

  parent reply	other threads:[~2014-04-09  8:31 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-04-09  8:29 [PATCH 0/7] Updated MIPI sequence for BYT Shobhit Kumar
2014-04-09  8:29 ` [PATCH 1/7] drm/i915: Program Rcomp and band gap reset everytime we resume from power gate Shobhit Kumar
2014-04-09  8:29 ` [PATCH 2/7] drm/i915: Enable MIPI port before the plane and pipe enable Shobhit Kumar
2014-04-09  8:29 ` [PATCH 3/7] drm/i915: Disable DPOunit clock gating Shobhit Kumar
2014-04-09  8:29 ` Shobhit Kumar [this message]
2014-04-09  8:29 ` [PATCH 5/7] drm/i915: Panel commands can be sent only when clock is in LP11 Shobhit Kumar
2014-04-09  8:29 ` [PATCH 6/7] drm/i915: Send DPI command explicitely in LP mode Shobhit Kumar
2014-04-09  8:29 ` [PATCH 7/7] drm/i915: Enable RANDOM resolution support for MIPI panels Shobhit Kumar
2014-04-09 14:51 ` [PATCH 0/7] Updated MIPI sequence for BYT Daniel Vetter
2014-04-09 16:01   ` Kumar, Shobhit
2014-04-09 16:50     ` Daniel Vetter

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