Re: [PATCH 45/71] drm/i915/chv: Streamline CHV forcewake stuff

Deepak S
2014-04-09T18:38:10Z

On Wednesday 09 April 2014 11:17 PM, Ville Syrjälä wrote:
> On Wed, Apr 09, 2014 at 06:02:36PM +0200, Daniel Vetter wrote:
>> On Wed, Apr 09, 2014 at 01:28:43PM +0300, ville.syrjala@linux.intel.com wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> Streamline the CHV forcewake functions just like was done for VLV.
>>>
>>> This will also fix a bug in accessing the common well registers,
>>> where we'd end up trying to wake up the wells too many times
>>> since we'd call force_wake_get/put twice per register access, with
>>> FORCEFAKE_ALL both times.
>>>
>>> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Ugh ... any chance this would make sense squashed in as a fixup into an
>> earlier patch? If it's too hairy I'm ok with this as-is.
> It could be squashed into patch 28 which introduces this code. I don't
> think there were other patches that touch this piece code. I have no
> objection to squashing. Deepak, any objections?

Nope. I am Ok with squashing the patch.

>> -Daniel
>>
>>> ---
>>> drivers/gpu/drm/i915/intel_uncore.c | 88 ++++++++++++++-----------------------
>>> 1 file changed, 32 insertions(+), 56 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>>> index ccad770..59293b3 100644
>>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>>> @@ -618,35 +618,22 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>>> unsigned fwengine = 0; \
>>> REG_READ_HEADER(x); \
>>> if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
>>> - fwengine = FORCEWAKE_RENDER; \
>>> - } \
>>> - else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
>>> - fwengine = FORCEWAKE_MEDIA; \
>>> - } \
>>> - else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
>>> - fwengine = FORCEWAKE_ALL; \
>>> - } \
>>> - if (FORCEWAKE_RENDER & fwengine) { \
>>> - if (dev_priv->uncore.fw_rendercount++ == 0) \
>>> - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
>>> - fwengine); \
>>> - } \
>>> - if (FORCEWAKE_MEDIA & fwengine) { \
>>> - if (dev_priv->uncore.fw_mediacount++ == 0) \
>>> - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
>>> - fwengine); \
>>> + if (dev_priv->uncore.fw_rendercount == 0) \
>>> + fwengine = FORCEWAKE_RENDER; \
>>> + } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
>>> + if (dev_priv->uncore.fw_mediacount == 0) \
>>> + fwengine = FORCEWAKE_MEDIA; \
>>> + } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
>>> + if (dev_priv->uncore.fw_rendercount == 0) \
>>> + fwengine |= FORCEWAKE_RENDER; \
>>> + if (dev_priv->uncore.fw_mediacount == 0) \
>>> + fwengine |= FORCEWAKE_MEDIA; \
>>> } \
>>> + if (fwengine) \
>>> + dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
>>> val = __raw_i915_read##x(dev_priv, reg); \
>>> - if (FORCEWAKE_RENDER & fwengine) { \
>>> - if (--dev_priv->uncore.fw_rendercount == 0) \
>>> - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
>>> - fwengine); \
>>> - } \
>>> - if (FORCEWAKE_MEDIA & fwengine) { \
>>> - if (--dev_priv->uncore.fw_mediacount == 0) \
>>> - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
>>> - fwengine); \
>>> - } \
>>> + if (fwengine) \
>>> + dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
>>> REG_READ_FOOTER; \
>>> }
>>>
>>> @@ -780,38 +767,27 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
>>> static void \
>>> chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
>>> unsigned fwengine = 0; \
>>> - bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
>>> + bool shadowed = is_gen8_shadowed(dev_priv, reg); \
>>> REG_WRITE_HEADER; \
>>> - if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
>>> - fwengine = FORCEWAKE_RENDER; \
>>> - } \
>>> - else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
>>> - fwengine = FORCEWAKE_MEDIA; \
>>> - } \
>>> - else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
>>> - fwengine = FORCEWAKE_ALL; \
>>> - } \
>>> - if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
>>> - if (dev_priv->uncore.fw_rendercount++ == 0) \
>>> - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
>>> - fwengine); \
>>> - } \
>>> - if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
>>> - if (dev_priv->uncore.fw_mediacount++ == 0) \
>>> - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
>>> - fwengine); \
>>> + if (!shadowed) { \
>>> + if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
>>> + if (dev_priv->uncore.fw_rendercount == 0) \
>>> + fwengine = FORCEWAKE_RENDER; \
>>> + } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
>>> + if (dev_priv->uncore.fw_mediacount == 0) \
>>> + fwengine = FORCEWAKE_MEDIA; \
>>> + } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
>>> + if (dev_priv->uncore.fw_rendercount == 0) \
>>> + fwengine |= FORCEWAKE_RENDER; \
>>> + if (dev_priv->uncore.fw_mediacount == 0) \
>>> + fwengine |= FORCEWAKE_MEDIA; \
>>> + } \
>>> } \
>>> + if (fwengine) \
>>> + dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
>>> __raw_i915_write##x(dev_priv, reg, val); \
>>> - if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \
>>> - if (--dev_priv->uncore.fw_rendercount == 0) \
>>> - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
>>> - fwengine); \
>>> - } \
>>> - if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \
>>> - if (--dev_priv->uncore.fw_mediacount == 0) \
>>> - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
>>> - fwengine); \
>>> - } \
>>> + if (fwengine) \
>>> + dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
>>> REG_WRITE_FOOTER; \
>>> }
>>>
>>> --
>>> 1.8.3.2
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> --
>> Daniel Vetter
>> Software Engineer, Intel Corporation
>> +41 (0) 79 365 57 48 - http://blog.ffwll.ch