[PATCH 30/71] drm/i915/chv: Enable PM interrupts when we in CHV turbo initialize sequence.

ville.syrjala
2014-04-09T10:30:57Z

From: Deepak S <deepak.s@intel.com>

v2: Mass rename of the dev_priv->rps variables in upstream.

Signed-off-by: Deepak S <deepak.s@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_pm.c | 43 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4217576..392731a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3155,6 +3155,28 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
}

+static void gen8_disable_rps_interrupts(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
+ I915_WRITE(GEN8_GT_IER(2),
+ I915_READ(GEN8_GT_IER(2)) & ~GEN6_PM_RPS_EVENTS);
+
+ spin_lock_irq(&dev_priv->irq_lock);
+ dev_priv->rps.pm_iir = 0;
+ spin_unlock_irq(&dev_priv->irq_lock);
+
+ I915_WRITE(GEN8_GT_IIR(2), I915_READ(GEN8_GT_IIR(2)));
+
+ /* Disable Turbo in control register */
+ I915_WRITE(GEN6_RP_CONTROL, 0);
+
+ /* Set the Freq to RPe */
+ valleyview_set_rps(dev, dev_priv->rps.efficient_freq);
+
+}
+
static void gen6_disable_rps_interrupts(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3190,6 +3212,8 @@ static void cherryview_disable_rps(struct drm_device *dev)

I915_WRITE(GEN6_RC_CONTROL, 0);

+ gen8_disable_rps_interrupts(dev);
+
if (dev_priv->vlv_pctx) {
drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
dev_priv->vlv_pctx = NULL;
@@ -3238,6 +3262,23 @@ int intel_enable_rc6(const struct drm_device *dev)
return INTEL_RC6_ENABLE;
}

+static void gen8_enable_rps_interrupts(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ /* Clear out any stale interrupts first */
+ spin_lock_irq(&dev_priv->irq_lock);
+ WARN_ON(dev_priv->rps.pm_iir);
+ I915_WRITE(GEN8_GT_IIR(2), I915_READ(GEN8_GT_IIR(2)));
+ dev_priv->pm_irq_mask &= ~GEN6_PM_RPS_EVENTS;
+ I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
+ spin_unlock_irq(&dev_priv->irq_lock);
+
+ I915_WRITE(GEN8_GT_IER(2), GEN6_PM_RPS_EVENTS);
+ /* only unmask PM interrupts we need. Mask all others. */
+ I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PM_RPS_EVENTS);
+}
+
static void gen6_enable_rps_interrupts(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3761,6 +3802,8 @@ static void cherryview_enable_rps(struct drm_device *dev)

valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);

+ gen8_enable_rps_interrupts(dev);
+
gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
}

--
1.8.3.2