From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH] drm/i915/vlv: assert and de-assert sideband reset on resume Date: Fri, 11 Apr 2014 20:23:22 +0300 Message-ID: <1397237002.25357.5.camel@intelbox> References: <1397235616-25925-1-git-send-email-jbarnes@virtuousgeek.org> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2108666333==" Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id ABB256E403 for ; Fri, 11 Apr 2014 10:23:25 -0700 (PDT) In-Reply-To: <1397235616-25925-1-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============2108666333== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-w7JxNmxb33zhBlOUy47K" --=-w7JxNmxb33zhBlOUy47K Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 2014-04-11 at 10:00 -0700, Jesse Barnes wrote: > This is a bit like the CMN reset de-assert we do in DPIO_CTL, except > that it resets the whole common lane section of the PHY. This is > required on machines where the BIOS doesn't do this for us on resume to > properly re-calibrate and get the PHY ready to transmit data. >=20 > Without this patch, such machines won't resume correctly much of the time= , > with the symptom being a 'port ready' timeout and/or a link training > failure. >=20 > I'm open to better suggestions on how to do the power well toggle, with > the existing code it looks like I'd have to walk through a bunch of > power domains looking for a match, then call a generic function which > will warn. I'd prefer to just expose the specific domains directly for > low level platform code like this. The power_well->sync_hw() handler looks like a good place for such things. It will get called from intel_power_domains_init_hw(), which is later than then the uncore sanitize functions, but then again if it's really needed that early then intel_power_domains_init_hw() should be moved earlier too.. --Imre >=20 > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/intel_pm.c | 4 ++-- > drivers/gpu/drm/i915/intel_uncore.c | 19 +++++++++++++++++++ > 2 files changed, 21 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index fa00185..3afd0bc 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5454,8 +5454,8 @@ static bool i9xx_always_on_power_well_enabled(struc= t drm_i915_private *dev_priv, > return true; > } > =20 > -static void vlv_set_power_well(struct drm_i915_private *dev_priv, > - struct i915_power_well *power_well, bool enable) > +void vlv_set_power_well(struct drm_i915_private *dev_priv, > + struct i915_power_well *power_well, bool enable) > { > enum punit_power_well power_well_id =3D power_well->data; > u32 mask; > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/i= ntel_uncore.c > index 2a72bab..f1abd2d 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -363,6 +363,9 @@ static void intel_uncore_forcewake_reset(struct drm_d= evice *dev, bool restore) > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); > } > =20 > +void vlv_set_power_well(struct drm_i915_private *dev_priv, > + struct i915_power_well *power_well, bool enable); > + > void intel_uncore_early_sanitize(struct drm_device *dev) > { > struct drm_i915_private *dev_priv =3D dev->dev_private; > @@ -381,6 +384,22 @@ void intel_uncore_early_sanitize(struct drm_device *= dev) > DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); > } > =20 > + /* > + * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: > + * Need to assert and de-assert PHY SB reset by gating the common > + * lane power, then un-gating it. > + * Simply ungating isn't enough to reset the PHY enough to get > + * ports and lanes running. > + */ > + if (IS_VALLEYVIEW(dev)) { > + struct i915_power_well cmn_well =3D { > + .data =3D PUNIT_POWER_WELL_DPIO_CMN_BC > + }; > + > + vlv_set_power_well(dev_priv, &cmn_well, false); > + vlv_set_power_well(dev_priv, &cmn_well, true); > + } > + > /* clear out old GT FIFO errors */ > if (IS_GEN6(dev) || IS_GEN7(dev)) > __raw_i915_write32(dev_priv, GTFIFODBG, --=-w7JxNmxb33zhBlOUy47K Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTSCUKAAoJEORIIAnNuWDFOrIIAIwjUtttrg8k/puXo/064YVS QX8y4s5wTT3+e0LbJ0v+7iVvEEFMpcGsqdHtshzF033bskW6XMXR03fS0MsJvIyk MikeiWuo869cuq6sq/N0RgdyLP7xG5aLcHm0Iz+i5rg9wW5IAkFuv0amWBgtPhCt nyE2dOIf8DTvGFFH3TL0580IBWoTkUZUowmpizZhuaw8jLP5qkG2vUFNeMSVkUuC cBajyWM9H5MN33bhpE1py4ElTL4lry0W/4T81EH/lYRvaZcwbRKfswK/5Z0Wg6F0 0Grl9tL41d6+pULwnPcZT0eONYJ1Ap9WrlnZ5i7T9sq+GZifNb4vz/QiyhMwxF4= =LBUb -----END PGP SIGNATURE----- --=-w7JxNmxb33zhBlOUy47K-- --===============2108666333== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============2108666333==--