From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 49/71] drm/i915/chv: Add CHV display support Date: Tue, 15 Apr 2014 18:56:28 +0300 Message-ID: <1397577388.3082.0.camel@intelbox> References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com> <1397039349-10639-50-git-send-email-ville.syrjala@linux.intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1360967347==" Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 91EC36E91C for ; Tue, 15 Apr 2014 08:58:19 -0700 (PDT) In-Reply-To: <1397039349-10639-50-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1360967347== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-N1g754IyWYkGMge63z+N" --=-N1g754IyWYkGMge63z+N Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2014-04-09 at 13:28 +0300, ville.syrjala@linux.intel.com wrote: > From: Rafael Barbalho >=20 > Add support for the third pipe in cherrview >=20 > Signed-off-by: Rafael Barbalho > [vsyrjala: slightly massaged the patch] > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 With the formatting fix from Jani: Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/i915_drv.c | 7 +++++++ > drivers/gpu/drm/i915/i915_reg.h | 11 ++++++++--- > 2 files changed, 15 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_= drv.c > index 2415fa2..c5e9fa8 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -49,6 +49,12 @@ static struct drm_driver driver; > .dpll_md_offsets =3D { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \ > .palette_offsets =3D { PALETTE_A_OFFSET, PALETTE_B_OFFSET } > =20 > +#define GEN_CHV_PIPEOFFSETS \ > + .pipe_offsets =3D { PIPE_A_OFFSET, PIPE_B_OFFSET, CHV_PIPE_C_OFFS= ET }, \ > + .trans_offsets =3D { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, CH= V_TRANSCODER_C_OFFSET, }, \ > + .dpll_offsets =3D { DPLL_A_OFFSET, DPLL_B_OFFSET, CHV_DPLL_C_OFFS= ET }, \ > + .dpll_md_offsets =3D { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, CHV_DP= LL_C_MD_OFFSET }, \ > + .palette_offsets =3D { PALETTE_A_OFFSET, PALETTE_B_OFFSET, CHV_PA= LETTE_C_OFFSET } > =20 > static const struct intel_device_info intel_i830_info =3D { > .gen =3D 2, .is_mobile =3D 1, .cursor_needs_physical =3D 1, .num_pipes = =3D 2, > @@ -286,6 +292,7 @@ static const struct intel_device_info intel_cherryvie= w_info =3D { > .ring_mask =3D RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > .is_valleyview =3D 1, > .display_mmio_offset =3D VLV_DISPLAY_BASE, > + GEN_CHV_PIPEOFFSETS, > }; > =20 > /* > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 7587752..3831d84 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1430,6 +1430,7 @@ enum punit_power_well { > */ > #define DPLL_A_OFFSET 0x6014 > #define DPLL_B_OFFSET 0x6018 > +#define CHV_DPLL_C_OFFSET 0x6030 > #define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \ > dev_priv->info.display_mmio_offset) > =20 > @@ -1521,6 +1522,7 @@ enum punit_power_well { > =20 > #define DPLL_A_MD_OFFSET 0x601c /* 965+ only */ > #define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */ > +#define CHV_DPLL_C_MD_OFFSET 0x603c > #define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \ > dev_priv->info.display_mmio_offset) > =20 > @@ -1717,6 +1719,7 @@ enum punit_power_well { > */ > #define PALETTE_A_OFFSET 0xa000 > #define PALETTE_B_OFFSET 0xa800 > +#define CHV_PALETTE_C_OFFSET 0xc000 > #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \ > dev_priv->info.display_mmio_offset) > =20 > @@ -2206,6 +2209,7 @@ enum punit_power_well { > #define TRANSCODER_A_OFFSET 0x60000 > #define TRANSCODER_B_OFFSET 0x61000 > #define TRANSCODER_C_OFFSET 0x62000 > +#define CHV_TRANSCODER_C_OFFSET 0x63000 > #define TRANSCODER_EDP_OFFSET 0x6f000 > =20 > #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - = \ > @@ -3533,9 +3537,10 @@ enum punit_power_well { > #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 > #define PIPESTAT_INT_STATUS_MASK 0x0000ffff > =20 > -#define PIPE_A_OFFSET 0x70000 > -#define PIPE_B_OFFSET 0x71000 > -#define PIPE_C_OFFSET 0x72000 > +#define PIPE_A_OFFSET 0x70000 > +#define PIPE_B_OFFSET 0x71000 > +#define PIPE_C_OFFSET 0x72000 > +#define CHV_PIPE_C_OFFSET 0x74000 > /* > * There's actually no pipe EDP. Some pipe registers have > * simply shifted from the pipe to the transcoder, while --=-N1g754IyWYkGMge63z+N Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTTVasAAoJEORIIAnNuWDFAaAIAKc7cVZxgkfiyy9r+vHrPgFV qnxaL8UBUl2/fS8sfhx4IpFi1Um+0b9lIrZHd4Z4oNyxIiLB45ECz+UQv4ubGeQ+ JQRuPAuocbe5POimXteWB9K2CJ56RVYtfgApOmIpCL9kyLyKIsAv96tjjGHnyknQ PzI/MfauZJQq5OdvmuWmLkH2g12Y7xoRbunW/ljld5yL7rCFNB1VVuLxtXDBNsZT Gz/famOcY0urjxvHINPGvJNyvh4yu6ClpuUjVzVLxrtw94D+VkjsqnCezdmWELbF 9CDdmSklOoGI17PyFbTihPb7ioDXaerA1CJ0WFQjqej97zsXI9lXflrgllFprwk= =+cas -----END PGP SIGNATURE----- --=-N1g754IyWYkGMge63z+N-- --===============1360967347== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1360967347==--