From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH v2 14/25] drm/i915: sanitize enable_rc6 option Date: Wed, 16 Apr 2014 15:37:49 +0300 Message-ID: <1397651869.4215.5.camel@intelbox> References: <1397496286-29649-1-git-send-email-imre.deak@intel.com> <1397496286-29649-15-git-send-email-imre.deak@intel.com> <20140416122805.GF18465@intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1597770292==" Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id EB6F66E385 for ; Wed, 16 Apr 2014 05:37:59 -0700 (PDT) In-Reply-To: <20140416122805.GF18465@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ville =?ISO-8859-1?Q?Syrj=E4l=E4?= Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1597770292== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-gvKrUciRzd3d3V/WK40y" --=-gvKrUciRzd3d3V/WK40y Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2014-04-16 at 15:28 +0300, Ville Syrj=C3=A4l=C3=A4 wrote: > On Mon, Apr 14, 2014 at 08:24:35PM +0300, Imre Deak wrote: > > Atm, an invalid enable_rc6 module option will be silently ignored, so > > emit an info message about it. Doing an early sanitization we can also > > reuse intel_enable_rc6() in a follow-up patch to see if RC6 is actually > > enabled. Currently the caller would have to filter a non-zero return > > value based on the platform we are running on. For example on VLV with > > i915.enable_rc6 set to 2, RC6 won't be enabled but atm > > intel_enable_rc6() would still return 2 in this case. > >=20 > > Signed-off-by: Imre Deak > > --- > > drivers/gpu/drm/i915/intel_pm.c | 27 ++++++++++++++++++++++++--- > > 1 file changed, 24 insertions(+), 3 deletions(-) > >=20 > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index a56f6b1..89fe0a7 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3262,15 +3262,29 @@ static void intel_print_rc6_info(struct drm_dev= ice *dev, u32 mode) > > (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); > > } > > =20 > > -int intel_enable_rc6(const struct drm_device *dev) > > +static int sanitize_rc6_option(const struct drm_device *dev, int enabl= e_rc6) > > { > > /* No RC6 before Ironlake */ > > if (INTEL_INFO(dev)->gen < 5) > > return 0; > > =20 > > /* Respect the kernel parameter if it is set */ > > - if (i915.enable_rc6 >=3D 0) > > - return i915.enable_rc6; > > + if (enable_rc6 >=3D 0) { > > + int mask =3D 0; > > + > > + if (IS_BROADWELL(dev) || IS_HASWELL(dev) || > > + IS_VALLEYVIEW(dev) || IS_IRONLAKE_M(dev)) > > + mask =3D INTEL_RC6_ENABLE; > > + else if (INTEL_INFO(dev)->gen >=3D 6) > > + mask =3D INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | > > + INTEL_RC6pp_ENABLE; >=20 > You forgot ILK.=20 For desktop ILK intel_enable_gt_powersave() will keep RC6 disabled, so the above is correct based on that. > Also this would seem simpler: >=20 > if (SNB|IVB) > mask =3D rc6 | rc6p | rc6pp; > else > mask =3D rc6; Ok, can rewrite it with the above exception for desktop ILK. --Imre >=20 > > + > > + if ((enable_rc6 & mask) !=3D enable_rc6) > > + DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n", > > + enable_rc6, enable_rc6 & mask, mask); > > + > > + return enable_rc6 & mask; > > + } > > =20 > > /* Disable RC6 on Ironlake */ > > if (INTEL_INFO(dev)->gen =3D=3D 5) > > @@ -3282,6 +3296,11 @@ int intel_enable_rc6(const struct drm_device *de= v) > > return INTEL_RC6_ENABLE; > > } > > =20 > > +int intel_enable_rc6(const struct drm_device *dev) > > +{ > > + return i915.enable_rc6; > > +} > > + > > static void gen6_enable_rps_interrupts(struct drm_device *dev) > > { > > struct drm_i915_private *dev_priv =3D dev->dev_private; > > @@ -4496,6 +4515,8 @@ static void intel_init_emon(struct drm_device *de= v) > > =20 > > void intel_init_gt_powersave(struct drm_device *dev) > > { > > + i915.enable_rc6 =3D sanitize_rc6_option(dev, i915.enable_rc6); > > + > > if (IS_VALLEYVIEW(dev)) > > valleyview_setup_pctx(dev); > > } > > --=20 > > 1.8.4 > >=20 > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx >=20 --=-gvKrUciRzd3d3V/WK40y Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTTnmdAAoJEORIIAnNuWDFmSYH/2DIBvI5rOMvswoZgxtCkbQM 8b5Uv2qjPG4DfUVyY6PsDTBYSyQgtzglQgoZE9OuyzSfeHkotWS8+ofQB7ObTaoN R3yWt7+cJcIgQhiW3RQy/yYKh0pIK6SgZZYvXFMmQjCgvroBfzKXDb/pKHpwIp1d JkSchv3OFjTz3cWuaMQ8Fidpp6cgjPzzXWTEvnQM16lCUhUk/PH/eDcmHtVkeObC /9e0cE9H8qZPtzjGEyPXiN4M9z2mtEFsom2dIgjNrsEs4xxuSmmjQZo2fw7QXYfA d5+9Q9TnwcuWmPVadKH3L9G5y9P4c3/F+qd4pEAP6KpJ4OZwFfuj8KsSj7JyRF4= =3Bnw -----END PGP SIGNATURE----- --=-gvKrUciRzd3d3V/WK40y-- --===============1597770292== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1597770292==--