From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH V3 1/6] drm/i915: Split the BDW device definition to prepare for dual BSD rings on BDW GT3 Date: Wed, 16 Apr 2014 17:14:18 +0300 Message-ID: <1397657658.4215.15.camel@intelbox> References: <1397616077-1125-1-git-send-email-yakui.zhao@intel.com> <1397616077-1125-2-git-send-email-yakui.zhao@intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1338852067==" Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 3B1DD6E24F for ; Wed, 16 Apr 2014 07:14:46 -0700 (PDT) In-Reply-To: <1397616077-1125-2-git-send-email-yakui.zhao@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Zhao Yakui Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1338852067== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-FI8F54LlnSVr5FnYoGc7" --=-FI8F54LlnSVr5FnYoGc7 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2014-04-16 at 10:41 +0800, Zhao Yakui wrote: > Based on the hardware spec, the BDW GT3 has the different configuration > with the BDW GT1/GT2. So split the BDW device info definition. > This is to do the preparation for adding the Dual BSD rings on BDW GT3 ma= chine. >=20 > V1->V2: Follow Daniel's comment to pay attention to the stolen check for = BDW > in kernel/early-quirks.c >=20 > Signed-off-by: Zhao Yakui Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/i915_drv.c | 26 ++++++++++++++++++++++++-- > include/drm/i915_pciids.h | 22 +++++++++++++++++----- > 2 files changed, 41 insertions(+), 7 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_= drv.c > index 5d8250f..17fbbe5 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -279,6 +279,26 @@ static const struct intel_device_info intel_broadwel= l_m_info =3D { > GEN_DEFAULT_PIPEOFFSETS, > }; > =20 > +static const struct intel_device_info intel_broadwell_gt3d_info =3D { > + .gen =3D 8, .num_pipes =3D 3, > + .need_gfx_hws =3D 1, .has_hotplug =3D 1, > + .ring_mask =3D RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > + .has_llc =3D 1, > + .has_ddi =3D 1, > + .has_fbc =3D 1, > + GEN_DEFAULT_PIPEOFFSETS, > +}; > + > +static const struct intel_device_info intel_broadwell_gt3m_info =3D { > + .gen =3D 8, .is_mobile =3D 1, .num_pipes =3D 3, > + .need_gfx_hws =3D 1, .has_hotplug =3D 1, > + .ring_mask =3D RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > + .has_llc =3D 1, > + .has_ddi =3D 1, > + .has_fbc =3D 1, > + GEN_DEFAULT_PIPEOFFSETS, > +}; > + > /* > * Make sure any device matches here are from most specific to most > * general. For example, since the Quanta match is based on the subsyst= em > @@ -311,8 +331,10 @@ static const struct intel_device_info intel_broadwel= l_m_info =3D { > INTEL_HSW_M_IDS(&intel_haswell_m_info), \ > INTEL_VLV_M_IDS(&intel_valleyview_m_info), \ > INTEL_VLV_D_IDS(&intel_valleyview_d_info), \ > - INTEL_BDW_M_IDS(&intel_broadwell_m_info), \ > - INTEL_BDW_D_IDS(&intel_broadwell_d_info) > + INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \ > + INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \ > + INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \ > + INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info) > =20 > static const struct pci_device_id pciidlist[] =3D { /* aka */ > INTEL_PCI_IDS, > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h > index 940ece4..24f3cad 100644 > --- a/include/drm/i915_pciids.h > +++ b/include/drm/i915_pciids.h > @@ -223,14 +223,26 @@ > _INTEL_BDW_D(gt, 0x160A, info), /* Server */ \ > _INTEL_BDW_D(gt, 0x160D, info) /* Workstation */ > =20 > -#define INTEL_BDW_M_IDS(info) \ > +#define INTEL_BDW_GT12M_IDS(info) \ > _INTEL_BDW_M_IDS(1, info), \ > - _INTEL_BDW_M_IDS(2, info), \ > - _INTEL_BDW_M_IDS(3, info) > + _INTEL_BDW_M_IDS(2, info) > =20 > -#define INTEL_BDW_D_IDS(info) \ > +#define INTEL_BDW_GT12D_IDS(info) \ > _INTEL_BDW_D_IDS(1, info), \ > - _INTEL_BDW_D_IDS(2, info), \ > + _INTEL_BDW_D_IDS(2, info) > + > +#define INTEL_BDW_GT3M_IDS(info) \ > + _INTEL_BDW_M_IDS(3, info) > + > +#define INTEL_BDW_GT3D_IDS(info) \ > _INTEL_BDW_D_IDS(3, info) > =20 > +#define INTEL_BDW_M_IDS(info) \ > + INTEL_BDW_GT12M_IDS(info), \ > + INTEL_BDW_GT3M_IDS(info) > + > +#define INTEL_BDW_D_IDS(info) \ > + INTEL_BDW_GT12D_IDS(info), \ > + INTEL_BDW_GT3D_IDS(info) > + > #endif /* _I915_PCIIDS_H */ --=-FI8F54LlnSVr5FnYoGc7 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQEcBAABAgAGBQJTTpA6AAoJEORIIAnNuWDFCEMIAMk0+My4WtkYLK2XTSuseIp0 o0pDkhCLCC0PfE1tn8rlf101gdkez03w1CTEpNaxasN0vnAuGnUirHLBqTX0O5cM EzcA8cNRmjbQvOjb/vw9lPiPhJdcZ/w9luHJEH3X77fW6RYuI8Vm3pZRgu2fXg9p +YlDT0M2jN7T4X31Q25Mh86eun+cEMp9q4kp9WSH03pXZ/eayl6srwBceI7XvS3S LIgNre5p0QzvwJuXr7nWWYpjq3oih4NU8UICPiaIbgMNvSBTBIXp5k2z+PtKqhZ3 maBeUDdCOlYnH4JNBf2LaPdCnkqZrpbY7P9XMUj1PVk/Y0mCDVoAPJ7nyFuSXc8= =GRFq -----END PGP SIGNATURE----- --=-FI8F54LlnSVr5FnYoGc7-- --===============1338852067== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1338852067==--